Four full-adder modelsim project with testbench

4位加法器—verilog\adder4.cr.mti
..................\adder4.mpf
..................\adder4.v
..................\adder4_testbench.v
..................\chart\Thumbs.db
..................\.....\图2-7.bmp
..................\transcript
..................\vsim.wlf
..................\wave\adder4.bmp
..................\....\adder4_testbench.bmp
..................\....\Thumbs.db
..................\.ork\adder4\verilog.asm
..................\....\......\_primary.dat
..................\....\......\_primary.vhd
..................\....\......_testbench\verilog.asm
..................\....\................\_primary.dat
..................\....\................\_primary.vhd
..................\....\_info
..................\....\adder4
..................\....\adder4_testbench
..................\chart
..................\wave
..................\work
4位加法器—verilog

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