JPEG decoding (Verilog)

JPEG\fpga_jpeg\dct\dct.v
....\.........\...\dctu.v
....\.........\...\dctub.v
....\.........\...\..._bench\bench_top.v
....\.........\...\dct_cos_table.v
....\.........\...\dct_mac.v
....\.........\...\dct_syn.v
....\.........\...\fdct.v
....\.........\...\huffman\bench\bench_top.v
....\.........\...\.......\.....\generic_dpram.v
....\.........\...\.......\.....\generic_fifo_lfsr.v
....\.........\...\.......\.....\lfsr.v
....\.........\...\.......\.....\timescale.v
....\.........\...\.......\huffman_dec.v
....\.........\...\.......\huffman_dec.v.bak
....\.........\...\.......\huffman_enc.v
....\.........\...\.......\huffman_tables.v
....\.........\...\huffman_tables.v
....\.........\...\rtl_sim\Makefile.txt
....\.........\...\timescale.v
....\.........\...\zigzag.v
....\.........\jpeg\bench_top\jpeg_encoder.v
....\.........\....\dct.v
....\.........\....\dctu.v
....\.........\....\dctu.v.bak
....\.........\....\dctub.v
....\.........\....\dct_cos_table.v
....\.........\....\dct_mac.v
....\.........\....\dct_syn.v
....\.........\....\div_su.v
....\.........\....\div_uu.v
....\.........\....\fdct.v
....\.........\....\huffman_enc.v
....\.........\....\huffman_enc.v.bak
....\.........\....\huffman_tables.v
....\.........\....\jpeg_encoder.v
....\.........\....\jpeg_encoder.v.bak
....\.........\....\jpeg_qnr.v
....\.........\....\jpeg_rle.v
....\.........\....\jpeg_rle1.v
....\.........\....\jpeg_rzs.v
....\.........\....\sim\cds.lib
....\.........\....\...\hdl.var
....\.........\....\...\Makefile.txt
....\.........\....\zigzag.v
....\.........\qnr\attic\div.v
....\.........\...\.....\div_us.v
....\.........\...\.....\ro_cnt.v
....\.........\...\.....\ud_cnt.v
....\.........\...\bench\bench_div_top.v
....\.........\...\.....\bench_qnr_top.v
....\.........\...\.....\timescale.v
....\.........\...\div_su.v
....\.........\...\div_uu.v
....\.........\...\jpeg_qnr.v
....\.........\rgb2ycrcb\modelsim.ini
....\.........\.........\rgb2ycrcb\_info
....\.........\.........\rgb2ycrcb.mpf
....\.........\.........\rgb2ycrcb.v
....\.........\.........\rgb2ycrcb_testbench.v
....\.........\.........\rgb2ycrcb_webAddress.txt
....\.........\.........\tcl_stacktrace.txt
....\.........\.........\transcript
....\.........\.........\work\_info
....\.........\.un_length_coding\attic\jpeg_rle2.v
....\.........\.................\bench\bench.v
....\.........\.................\jpeg_rle.v
....\.........\.................\jpeg_rle1.v
....\.........\.................\jpeg_rzs.v
....\.........\dct\huffman\bench
....\.........\...\dct_bench
....\.........\...\huffman
....\.........\...\rtl_sim
....\.........\jpeg\bench_top
....\.........\....\sim
....\.........\qnr\attic
....\.........\...\bench
....\.........\rgb2ycrcb\rgb2ycrcb
....\.........\.........\work
....\.........\.un_length_coding\attic
....\.........\.................\bench
....\.........\dct
....\.........\jpeg
....\.........\qnr
....\.........\rgb2ycrcb
....\.........\run_length_coding
....\fpga_jpeg
JPEG

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