FPGA-based controller design of sdram (VERILOG language)

基于FPGA对sdram控制器的设计（VERILOG语言）\sdram_control\doc\read_me.doc
..........................................\.............\...\SDRAM.doc
..........................................\.............\...\sdr_sdram.pdf
..........................................\.............\sim\altera_mf.v
..........................................\.............\...\Command.v
..........................................\.............\...\control_interface.v
..........................................\.............\...\mt48lc2m32b2.v
..........................................\.............\...\Params.v
..........................................\.............\...\sdram_test.cr.mti
..........................................\.............\...\sdram_test.mpf
..........................................\.............\...\sdram_test.wlf
..........................................\.............\...\sdram_test_tb.v
..........................................\.............\...\transcript
..........................................\.............\...\vsim.wlf
..........................................\.............\...\wave.do
..........................................\.............\...\.ork\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\verilog.asm
..........................................\.............\...\....\..........................................\_primary.dat
..........................................\.............\...\....\..........................................\_primary.vhd
..........................................\.............\...\....\.m@f_pll_reg\verilog.asm
..........................................\.............\...\....\............\_primary.dat
..........................................\.............\...\....\............\_primary.vhd
..........................................\.............\...\....\.....ram7x20_syn\verilog.asm
..........................................\.............\...\....\................\_primary.dat
..........................................\.............\...\....\................\_primary.vhd
..........................................\.............\...\....\.....stratixii_pll\verilog.asm
..........................................\.............\...\....\..................\_primary.dat
..........................................\.............\...\....\..................\_primary.vhd
..........................................\.............\...\....\............_pll\verilog.asm
..........................................\.............\...\....\................\_primary.dat
..........................................\.............\...\....\................\_primary.vhd
..........................................\.............\...\....\alt3pram\verilog.asm
..........................................\.............\...\....\........\_primary.dat
..........................................\.............\...\....\........\_primary.vhd
..........................................\.............\...\....\...accumulate\verilog.asm
..........................................\.............\...\....\.............\_primary.dat
..........................................\.............\...\....\.............\_primary.vhd
..........................................\.............\...\....\...cam\verilog.asm
..........................................\.............\...\....\......\_primary.dat
..........................................\.............\...\....\......\_primary.vhd
..........................................\.............\...\....\....dr_rx\verilog.asm
..........................................\.............\...\....\.........\_primary.dat
..........................................\.............\...\....\.........\_primary.vhd
..........................................\.............\...\....\.......tx\verilog.asm
..........................................\.............\...\....\.........\_primary.dat
..........................................\.............\...\....\.........\_primary.vhd
..........................................\.............\...\....\....lklock\verilog.asm
..........................................\.............\...\

• We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
• The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
• Please use Winrar for decompression tools
• If download fail, Try it againg or Feedback to us.
• If downloaded content did not match the introduction, Feedback to us，Confirm and will be refund.
• Before downloading, you can inquire through the uploaded person information

Nothing．