32-bit carry select adder, preset logic 0 and logic 1, the modules run in parallel, as long as through the carry bit selection logic 0 or logic 1 can improve the speed.

adder_32bits\.lso
............\adder_32bits.bld
............\adder_32bits.cel
............\adder_32bits.cmd_log
............\adder_32bits.ise
............\adder_32bits.ise_ISE_Backup
............\adder_32bits.lso
............\adder_32bits.ncd
............\adder_32bits.ngc
............\adder_32bits.ngd
............\adder_32bits.ngr
............\adder_32bits.ntrc_log
............\adder_32bits.pad
............\adder_32bits.par
............\adder_32bits.pcf
............\adder_32bits.prj
............\adder_32bits.restore
............\adder_32bits.stx
............\adder_32bits.syr
............\adder_32bits.twr
............\adder_32bits.twx
............\adder_32bits.ucf
............\adder_32bits.unroutes
............\adder_32bits.v
............\adder_32bits.xpi
............\adder_32bits.xst
............\adder_32bits_guide.ncd
............\adder_32bits_map.map
............\adder_32bits_map.mrp
............\adder_32bits_map.ncd
............\adder_32bits_map.ngm
............\adder_32bits_pad.csv
............\adder_32bits_pad.txt
............\adder_32bits_prev_built.ngd
............\adder_32bits_summary.html
............\adder_32bits_summary.xml
............\adder_32bits_tb.fdo
............\adder_32bits_tb.udo
............\adder_32bits_tb.v
............\adder_32bits_usage.xml
............\adder_4bits.prj
............\adder_4bits.stx
............\adder_4bits.v
............\adder_4bits.xst
............\conditional_adder_4bits.v
............\mux.prj
............\mux.stx
............\mux.v
............\mux.xst
............\transcript
............\vsim.wlf
............\work\adder_32bits\verilog.asm
............\....\............\_primary.dat
............\....\............\_primary.vhd
............\....\............_tb\verilog.asm
............\....\...............\_primary.dat
............\....\...............\_primary.vhd
............\....\......4bits\verilog.asm
............\....\...........\_primary.dat
............\....\...........\_primary.vhd
............\....\conditional_adder_4bits\verilog.asm
............\....\.......................\_primary.dat
............\....\.......................\_primary.vhd
............\....\glbl\transcript
............\....\....\verilog.asm
............\....\....\_primary.dat
............\....\....\_primary.vhd
............\....\mux\verilog.asm
............\....\...\_primary.dat
............\....\...\_primary.vhd
............\....\_info
............\xst\dump.xst\adder_32bits.prj\ntrc.scr
............\...\work\hdllib.ref
............\...\....\vlg0E\adder__32bits.bin
............\...\....\...10\conditional__adder__4bits.bin
............\...\....\...65\adder__4bits.bin
............\...\....\....6\mux.bin
............\_ngo\netlist.lst
............\.xmsgs\map.xmsgs
............\......\ngdbuild.xmsgs
............\......\par.xmsgs
............\......\trce.xmsgs
............\......\xst.xmsgs
............\xst\dump.xst\adder_32bits.prj\ngx\notopt
............\...\........\................\...\opt
............\...\........\................\ngx
............\...\........\adder_32bits.prj
............\...\work\vlg0E
............\...\....\vlg10
............\...\....\vlg65
............\...\....\vlg66
............\work\adder_32bits
............\....\adder_32bits_tb
............\....\adder_4bits
............\....\conditional_adder_4bits
............\....\glbl
............\....\mux
............\xst\dump.xst
............\...\projnav.tmp
............\...\work

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