State machine design a good example of hard work, VHDL language.Ｉthink it will help verilog　learners

状态机设计的例子\db\FSM.asm.qmsg
................\..\FSM.asm_labs.ddb
................\..\FSM.cbx.xml
................\..\FSM.cmp.cdb
................\..\FSM.cmp.hdb
................\..\FSM.cmp.kpt
................\..\FSM.cmp.logdb
................\..\FSM.cmp.rdb
................\..\FSM.cmp.tdb
................\..\FSM.cmp0.ddb
................\..\FSM.cmp2.ddb
................\..\FSM.dbp
................\..\FSM.db_info
................\..\FSM.eco.cdb
................\..\FSM.fit.qmsg
................\..\FSM.hier_info
................\..\FSM.hif
................\..\FSM.map.cdb
................\..\FSM.map.hdb
................\..\FSM.map.logdb
................\..\FSM.map.qmsg
................\..\FSM.pre_map.cdb
................\..\FSM.pre_map.hdb
................\..\FSM.psp
................\..\FSM.rtlv.hdb
................\..\FSM.rtlv_sg.cdb
................\..\FSM.rtlv_sg_swap.cdb
................\..\FSM.sgdiff.cdb
................\..\FSM.sgdiff.hdb
................\..\FSM.signalprobe.cdb
................\..\FSM.sld_design_entry.sci
................\..\FSM.sld_design_entry_dsc.sci
................\..\FSM.smp_dump.txt
................\..\FSM.syn_hier_info
................\..\FSM.tan.qmsg
................\FSM.asm.rpt
................\FSM.done
................\FSM.fit.rpt
................\FSM.fit.smsg
................\FSM.fit.summary
................\FSM.flow.rpt
................\FSM.map.rpt
................\FSM.map.summary
................\FSM.pin
................\FSM.pof
................\FSM.qpf
................\FSM.qsf
................\FSM.qws
................\FSM.sof
................\FSM.tan.rpt
................\FSM.tan.summary
................\FSM.v
................\db
状态机设计的例子

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