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digital-clock-

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2012-11-26
  • Size : 158kb
  • Downloaded :0次
  • Author :西蟀
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
The code using verilog HDL language. Implementation is a digital stopwatch timer functions
Packet file list
(Preview for download)
典型实例3_1 数字跑表\实战训练3 数字跑表\project\.untf
....................\..................\.......\bitgen.ut
....................\..................\.......\paobiao.bgn
....................\..................\.......\paobiao.bit
....................\..................\.......\paobiao.bld
....................\..................\.......\paobiao.cmd_log
....................\..................\.......\paobiao.dhp
....................\..................\.......\paobiao.drc
....................\..................\.......\paobiao.ise
....................\..................\.......\paobiao.ise_ISE_Backup
....................\..................\.......\paobiao.lso
....................\..................\.......\paobiao.mrp
....................\..................\.......\paobiao.nc1
....................\..................\.......\paobiao.ncd
....................\..................\.......\paobiao.ngc
....................\..................\.......\paobiao.ngd
....................\..................\.......\paobiao.ngm
....................\..................\.......\paobiao.ngr
....................\..................\.......\paobiao.pad
....................\..................\.......\paobiao.pad_txt
....................\..................\.......\paobiao.par
....................\..................\.......\paobiao.pcf
....................\..................\.......\paobiao.placed_ncd_tracker
....................\..................\.......\paobiao.prj
....................\..................\.......\paobiao.routed_ncd_tracker
....................\..................\.......\paobiao.stx
....................\..................\.......\paobiao.syr
....................\..................\.......\paobiao.twr
....................\..................\.......\paobiao.twx
....................\..................\.......\paobiao.ut
....................\..................\.......\paobiao.v
....................\..................\.......\paobiao.xpi
....................\..................\.......\paobiao_last_par.ncd
....................\..................\.......\paobiao_map.ncd
....................\..................\.......\paobiao_map.ngm
....................\..................\.......\paobiao_pad.csv
....................\..................\.......\paobiao_pad.txt
....................\..................\.......\paobiao_summary.html
....................\..................\.......\paobiao_tb.ant
....................\..................\.......\paobiao_tb.fdo
....................\..................\.......\paobiao_tb.jhd
....................\..................\.......\paobiao_tb.tbw
....................\..................\.......\paobiao_tb.tfw
....................\..................\.......\paobiao_tb.udo
....................\..................\.......\paobiao_tb.xwv
....................\..................\.......\paobiao_tb.xwv_bak
....................\..................\.......\paobiao_tb_bencher.prj
....................\..................\.......\paobiao_tb_tb.v
....................\..................\.......\paobiao_tb_tb.v.bak
....................\..................\.......\paobiao_vhdl.prj
....................\..................\.......\transcript
....................\..................\.......\vsim.wlf
....................\..................\.......\work\glbl\verilog.asm
....................\..................\.......\....\....\_primary.dat
....................\..................\.......\....\....\_primary.vhd
....................\..................\.......\....\paobiao\verilog.asm
....................\..................\.......\....\.......\_primary.dat
....................\..................\.......\....\.......\_primary.vhd
....................\..................\.......\....\......._tb\verilog.asm
....................\..................\.......\....\..........\_primary.dat
....................\..................\.......\....\..........\_primary.vhd
....................\..................\.......\....\_info
....................\..................\.......\xst\work\hdllib.ref
....................\..................\.......\...\....\vlg73
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