The code is written using the VERILOG, used to implement the 4 x 4 keyboard scan.

key
...\dev
...\...\db
...\...\..\key.analyze_file.qmsg
...\...\..\key.asm.qmsg
...\...\..\key.cbx.xml
...\...\..\key.cmp.kpt
...\...\..\key.cmp.rdb
...\...\..\key.db_info
...\...\..\key.eco.cdb
...\...\..\key.eda.qmsg
...\...\..\key.fit.qmsg
...\...\..\key.hier_info
...\...\..\key.hif
...\...\..\key.lpc.html
...\...\..\key.lpc.rdb
...\...\..\key.lpc.txt
...\...\..\key.map.cdb
...\...\..\key.map.hdb
...\...\..\key.map.logdb
...\...\..\key.map.qmsg
...\...\..\key.pre_map.cdb
...\...\..\key.pre_map.hdb
...\...\..\key.rpp.qmsg
...\...\..\key.rtlv.hdb
...\...\..\key.rtlv_sg.cdb
...\...\..\key.rtlv_sg_swap.cdb
...\...\..\key.sgate.rvd
...\...\..\key.sgate_sm.rvd
...\...\..\key.sgdiff.cdb
...\...\..\key.sgdiff.hdb
...\...\..\key.sld_design_entry.sci
...\...\..\key.sld_design_entry_dsc.sci
...\...\..\key.smp_dump.txt
...\...\..\key.syn_hier_info
...\...\..\key.tan.qmsg
...\...\..\key.tis_db_list.ddb
...\...\..\prev_cmp_key.asm.qmsg
...\...\..\prev_cmp_key.eda.qmsg
...\...\..\prev_cmp_key.fit.qmsg
...\...\..\prev_cmp_key.map.qmsg
...\...\..\prev_cmp_key.qmsg
...\...\..\prev_cmp_key.tan.qmsg
...\...\incremental_db
...\...\..............\compiled_partitions
...\...\..............\...................\key.root_partition.map.kpt
...\...\..............\README
...\...\key.asm.rpt
...\...\key.bsf
...\...\key.done
...\...\key.eda.rpt
...\...\key.fit.rpt
...\...\key.fit.summary
...\...\key.flow.rpt
...\...\key.map.rpt
...\...\key.map.summary
...\...\key.pin
...\...\key.pof
...\...\key.qpf
...\...\key.qsf
...\...\key.tan.rpt
...\...\key.tan.summary
...\...\key_description.txt
...\...\key_nativelink_simulation.rpt
...\...\row_signal.bsf
...\...\simulation
...\...\..........\modelsim
...\...\..........\........\key.sft
...\...\..........\........\key.vo
...\...\..........\........\key_modelsim.xrf
...\...\..........\........\key_run_msim_rtl_verilog.do
...\...\..........\........\key_run_msim_rtl_verilog.do.bak
...\...\..........\........\key_run_msim_rtl_verilog.do.bak1
...\...\..........\........\key_run_msim_rtl_verilog.do.bak2
...\...\..........\........\key_run_msim_rtl_verilog.do.bak3
...\...\..........\........\key_v.sdo
...\...\..........\........\modelsim.ini
...\...\..........\........\msim_transcript
...\...\..........\........\rtl_work
...\...\..........\........\........\key
...\...\..........\........\........\...\verilog.prw
...\...\..........\........\........\...\verilog.psm
...\...\..........\........\........\...\_primary.dat
...\...\..........\........\........\...\_primary.dbs
...\...\..........\........\........\...\_primary.vhd
...\...\..........\........\........\key_top
...\...\..........\........\........\.......\verilog.prw
...\...\..........\........\........\.......\verilog.psm
...\...\..........\........\........\.......\_primary.dat
...\...\..........\........\........\.......\_primary.dbs
...\...\..........\........\........\.......\_primary.vhd
...\...\..........\........\........\row_signal
...\...\..........\........\........\..........\verilog.prw
...\...\..........\........\........\..........\verilog.psm
...\...\..........\........\........\..........\_primary.dat
...\...\..........\........\........\..........\_primary.dbs
...\...\..........\........\........\..........\_primary.vhd
...\...\..........\........\........\synchronizer
...\...\..........\........\........\............\verilog.prw
...\...\..........\........\........\............\verilog.psm

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