The basic digital circuit gates, register, fulladder, there is a washing machine control program

lab2(result)\screenshot(lab2)\4bit-ArithmeticUnit.jpg
............\................\4bit-lac_adder.JPG
............\................\alu.JPG
............\................\bit_slice.JPG
............\................\four_adder_subtractor.JPG
............\................\four_bit_shifter.JPG
............\................\nbit_logic_unit.JPG
............\................\nbit_mux.JPG
............\................\shift_control_logic.JPG
............\................\shift_rotate.JPG
............\................\Thumbs.db
............\ucf\alu.ucf
............\...\bit_slice.ucf
............\...\four_bit_adder_subtractor.ucf
............\...\four_bit_arithmetric.ucf
............\...\four_bit_lac.ucf
............\...\four_bit_lac_adder.ucf
............\...\four_bit_shifter.ucf
............\...\four_input_multiplexer.ucf
............\...\nbit_xor_contol.ucf
............\...\n_bit_2_input_mux.ucf
............\...\n_bit_adder.ucf
............\...\n_bit_logic_unit.ucf
............\...\shift_control_logic.ucf
............\...\shift_rotate.ucf
............\vhd(source and testbench)\ALU.ise
............\.........................\ALU.vhd
............\.........................\alu_tb.vhd
............\.........................\bit_slice.vhd
............\.........................\bit_slice_tb.vhd
............\.........................\four_bit_adder_subtractor.vhd
............\.........................\four_bit_arithmetric.vhd
............\.........................\four_bit_arithmetric_tb.vhd
............\.........................\four_bit_LAC.vhd
............\.........................\four_bit_LAC_adder.vhd
............\.........................\four_bit_lac_adder_tb.vhd
............\.........................\four_bit_shifter.vhd
............\.........................\four_bit_shifter_tb.vhd
............\.........................\four_input_multiplexer.vhd
............\.........................\four_input_mux_tb.vhd
............\.........................\full_adder.vhd
............\.........................\half_adder.vhd
............\.........................\inverter.vhd
............\.........................\nbit_xor_contol.vhd
............\.........................\n_bit_2_input_mux.vhd
............\.........................\n_bit_2_input_mux_tb.vhd
............\.........................\n_bit_adder.vhd
............\.........................\n_bit_adder_tb.vhd
............\.........................\n_bit_logic_unit.vhd
............\.........................\n_bit_logic_unit_tb.vhd
............\.........................\or_gate.vhd
............\.........................\shift_control_logic.vhd
............\.........................\shift_control_logic_tb.vhd
............\.........................\shift_rotate.vhd
............\.........................\shift_rotate_tb.vhd
............\.........................\test_four_bit_adder_subtractor.vhd
............\.........................\test_fout_bit_adder_subtractor.vhd
............\.........................\two_input_and.vhd
............\.........................\two_input_multiplexer.vhd
............\.........................\two_input_or.vhd
............\.........................\two_input_xor.vhd
............\.........................\__projnav\ALU.gfl
............\.........................\.........\createTB.err
...3(preparatory)\d_flipflop.vhd
.................\d_flipflop_tb.vhd
.................\four_bit_Feedback.vhd
.................\four_bit_Feedback_tb.vhd
.................\four_input_multiplexer.vhd
.................\lab3.ise
.................\nbit_reg.vhd
.................\nbit_reg_control_triout.vhd
.................\nbit_reg_tb.vhd
.................\nbit_reg_with_control.vhd
.................\nbit_shiftreg.vhd
.................\nbit_shiftreg_par_load.vhd
.................\nbit_shiftreg_par_tb.vhd
.................\nbit_shiftreg_tb.vhd
.................\nbit_tri_buff.vhd
.................\nbit_tri_buff_tb.vhd
.................\nbit_twisted_ringcou.vhd
.................\nbit_twisted_tb.vhd
.................\nbit_universal_shiftreg.vhd
.................\nbit_universal_tb.vhd

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