read and write languages LCD verilog code, including the entire project

LCD实验\Project\LCD_1602\constraint\LCD_Top.pdc
.......\.......\........\designer\impl1\designer.log
.......\.......\........\........\.....\LCD_Top.adb
.......\.......\........\........\.....\........dtf\verify.log
.......\.......\........\........\.....\LCD_Top.ide_des
.......\.......\........\........\.....\LCD_Top.pdb
.......\.......\........\........\.....\LCD_Top.pdb.depends
.......\.......\........\........\.....\LCD_Top.tcl
.......\.......\........\........\.....\LCD_Top_ba.sdf
.......\.......\........\........\.....\LCD_Top_ba.v
.......\.......\........\hdl\Clock_Gen.v
.......\.......\........\...\hdlsynchk.tcl
.......\.......\........\...\LCD_Driver.v
.......\.......\........\...\LCD_Top.v
.......\.......\........\LCD_1602.prj
.......\.......\........\LCD_1602.prj.convert.8.1.bak
.......\.......\........\simulation\meminit.dat
.......\.......\........\..........\modelsim.ini
.......\.......\........\..........\modelsim.ini.sav
.......\.......\........\.martgen\PLL_1M\PLL_1M.cxf
.......\.......\........\........\......\PLL_1M.gen
.......\.......\........\........\......\PLL_1M.log
.......\.......\........\........\......\PLL_1M.v
.......\.......\........\........\PLL_1M_work.ixf
.......\.......\........\........\smartgen.aws
.......\.......\........\.ynthesis\.recordref
.......\.......\........\.........\LCD_Top.areasrr
.......\.......\........\.........\LCD_Top.edn
.......\.......\........\.........\LCD_Top.fse
.......\.......\........\.........\LCD_Top.htm
.......\.......\........\.........\LCD_Top.map
.......\.......\........\.........\LCD_Top.sap
.......\.......\........\.........\LCD_Top.sdf
.......\.......\........\.........\LCD_Top.srd
.......\.......\........\.........\LCD_Top.srm
.......\.......\........\.........\LCD_Top.srr
.......\.......\........\.........\LCD_Top.srs
.......\.......\........\.........\LCD_Top.tlg
.......\.......\........\.........\LCD_Top_sdc.sdc
.......\.......\........\.........\LCD_Top_syn.prj
.......\.......\........\.........\stdout.log
.......\.......\........\.........\.yntmp\LCD_Top.msg
.......\.......\........\.........\......\LCD_Top.plg
.......\.......\........\.........\......\LCD_Top_flink.htm
.......\.......\........\.........\......\LCD_Top_srr.htm
.......\.......\........\.........\......\LCD_Top_toc.htm
.......\.......\........\.........\......\sap.log
.......\.......\........\.........\traplog.tlg
.......\.......\........\viewdraw\vf\project.lst
.......\.......\........\........\viewdraw.ini
.......\Source File\Clock_Gen.v
.......\...........\LCD_Driver.v
.......\...........\LCD_Top.v
.......\Project\LCD_1602\designer\impl1\LCD_Top.dtf
.......\.......\........\........\.....\simulation
.......\.......\........\........\impl1
.......\.......\........\smartgen\PLL_1M
.......\.......\........\.ynthesis\syntmp
.......\.......\........\viewdraw\sch
.......\.......\........\........\sym
.......\.......\........\........\vf
.......\.......\........\........\wir
.......\.......\........\component
.......\.......\........\constraint
.......\.......\........\coreconsole
.......\.......\........\designer
.......\.......\........\hdl
.......\.......\........\phy_synthesis
.......\.......\........\simulation
.......\.......\........\smartgen
.......\.......\........\stimulus
.......\.......\........\synthesis
.......\.......\........\viewdraw
.......\.......\LCD_1602
.......\Project
.......\Source File
LCD实验

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