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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 576kb
  • Downloaded :0次
  • Author :Jun
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
Synchronous and asynchronous FIFO, VHDL implementation. We want to help.
Packet file list
(Preview for download)
FIFO\17819c8c-72d0-4130-a0db-ca01fe42e8b0\SFIFO_tb.vhd
....\....................................\sim.do
....\....................................\wave.do
....\266ec7ec-7779-4780-a9ba-8db4b4e46450\sfifo.vhd
....\....................................\transcript
....\30d4e845-8448-42fc-bd8d-ce6543759ac5\同步FIFO原理剖析.doc
....\575687b3-0cbf-4e1b-b3be-12766daa84f7\SFIFO.vhd
....\....................................\SFIFO_tb.vhd
....\f16bef58-0e24-400d-8e11-67dbf76df23c.pdf
....\17819c8c-72d0-4130-a0db-ca01fe42e8b0
....\266ec7ec-7779-4780-a9ba-8db4b4e46450
....\30d4e845-8448-42fc-bd8d-ce6543759ac5
....\575687b3-0cbf-4e1b-b3be-12766daa84f7
FIFO
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