9054 Verilog HDL timing control

9054 verilog\cmp_state.ini
............\command.v
............\control_interface.v
............\datacnt.v
............\.b\add_sub_ovb.tdf
............\..\altsyncram_k2j1.tdf
............\..\altsyncram_prf1.tdf
............\..\altsyncram_tji2.tdf
............\..\alt_synch_pipe_0e8.tdf
............\..\alt_synch_pipe_1e8.tdf
............\..\a_fefifo_30d.tdf
............\..\a_fefifo_80d.tdf
............\..\a_gray2bin_26b.tdf
............\..\a_graycounter_626.tdf
............\..\cmpr_5mh.tdf
............\..\cntr_5hi.tdf
............\..\cntr_68j.tdf
............\..\cntr_h5i.tdf
............\..\cntr_ifh.tdf
............\..\cntr_kua.tdf
............\..\cntr_rbk.tdf
............\..\dcfifo_egg1.tdf
............\..\decode_7ia.tdf
............\..\decode_ogi.tdf
............\..\dffpipe_oe9.tdf
............\..\dffpipe_qe9.tdf
............\..\dffpipe_re9.tdf
............\..\dpram_45v.tdf
............\..\mux_4eb.tdf
............\..\WITH_SDRAM_DAQ.asm.qmsg
............\..\WITH_SDRAM_DAQ.cbx.xml
............\..\WITH_SDRAM_DAQ.cmp.cdb
............\..\WITH_SDRAM_DAQ.cmp.hdb
............\..\WITH_SDRAM_DAQ.cmp.logdb
............\..\WITH_SDRAM_DAQ.cmp.rdb
............\..\WITH_SDRAM_DAQ.cmp.tdb
............\..\WITH_SDRAM_DAQ.cmp0.ddb
............\..\WITH_SDRAM_DAQ.dbp
............\..\WITH_SDRAM_DAQ.db_info
............\..\WITH_SDRAM_DAQ.eco.cdb
............\..\WITH_SDRAM_DAQ.fit.qmsg
............\..\WITH_SDRAM_DAQ.hier_info
............\..\WITH_SDRAM_DAQ.hif
............\..\WITH_SDRAM_DAQ.map.cdb
............\..\WITH_SDRAM_DAQ.map.hdb
............\..\WITH_SDRAM_DAQ.map.logdb
............\..\WITH_SDRAM_DAQ.map.qmsg
............\..\WITH_SDRAM_DAQ.pre_map.cdb
............\..\WITH_SDRAM_DAQ.pre_map.hdb
............\..\WITH_SDRAM_DAQ.psp
............\..\WITH_SDRAM_DAQ.pss
............\..\WITH_SDRAM_DAQ.rtlv.hdb
............\..\WITH_SDRAM_DAQ.rtlv_sg.cdb
............\..\WITH_SDRAM_DAQ.rtlv_sg_swap.cdb
............\..\WITH_SDRAM_DAQ.sgdiff.cdb
............\..\WITH_SDRAM_DAQ.sgdiff.hdb
............\..\WITH_SDRAM_DAQ.signalprobe.cdb
............\..\WITH_SDRAM_DAQ.sld_design_entry.sci
............\..\WITH_SDRAM_DAQ.sld_design_entry_dsc.sci
............\..\WITH_SDRAM_DAQ.smp_dump.txt
............\..\WITH_SDRAM_DAQ.syn_hier_info
............\..\WITH_SDRAM_DAQ.tan.qmsg
............\dpram16k_1to512_32.bsf
............\dpram16k_1to512_32.v
............\dpram16k_1to512_32_bb.v
............\fifo1k_32.bsf
............\fifo1k_32.v
............\fifo1k_32_bb.v
............\fifo1k_32_wave0.jpg
............\fifo1k_32_waveforms.html
............\Params.v
............\pll0.bsf
............\pll0.v
............\pll0_bb.v
............\plx_r.v
............\receiver.v
............\rec_src.v
............\sdr_data_path.v
............\sdr_sdram.v
............\WITH_SDRAM_DAQ.asm.rpt
............\WITH_SDRAM_DAQ.done
............\WITH_SDRAM_DAQ.fit.eqn
............\WITH_SDRAM_DAQ.fit.rpt
............\WITH_SDRAM_DAQ.fit.smsg
............\WITH_SDRAM_DAQ.fit.summary
............\WITH_SDRAM_DAQ.flow.rpt
............\WITH_SDRAM_DAQ.jdi
............\WITH_SDRAM_DAQ.map.eqn
............\WITH_SDRAM_DAQ.map.rpt
............\WITH_SDRAM_DAQ.map.smsg
............\WITH_SDRAM_DAQ.map.summary
............\WITH_SDRAM_DAQ.pin
............\WITH_SDRAM_DAQ.pof
............\WITH_SDRAM_DAQ.qpf
............\WITH_SDRAM_DAQ.qsf
............\WITH_SDRAM_DAQ.qsf.bak
............\WITH_SDRAM_DAQ.qws
............\WITH_SDRAM_DAQ.sof
............\WITH_SDRAM_DAQ.stp
............\WITH_SDRAM_DAQ.tan.rpt

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