Shift register with blockram achieve the development language for the verilog hdl

sim\testbench\tb.v
...\.........\clk_rst_gen.v
...\.........\glbl.v
...\cic.do
...\work\_info
...\....\clk_rst_gen\_primary.vhd
...\....\...........\verilog.asm
...\....\...........\_primary.dat
...\....\tb\_primary.vhd
...\....\..\verilog.asm
...\....\..\_primary.dat
...\....\dpram_block\_primary.vhd
...\....\...........\verilog.asm
...\....\...........\_primary.dat
...\....\shift_reg_module\_primary.vhd
...\....\................\verilog.asm
...\....\................\_primary.dat
...\....\glbl\_primary.vhd
...\....\....\verilog.asm
...\....\....\_primary.dat
...\qq.mpf
...\qq.cr.mti
用blockram实现移位寄存器.doc
src\shift_reg_module.v
...\dpram_block.v
.im\work\_temp
...\....\clk_rst_gen
...\....\tb
...\....\dpram_block
...\....\shift_reg_module
...\....\glbl
...\testbench
...\work
sim
src

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