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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 10kb
  • Downloaded :0次
  • Author :wkd
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
Adopted verilog language realizes sobel edge detection in image processing algorithm
Packet file list
(Preview for download)
sobel程序\abs.v
.........\data_grads.v
.........\fe_data3by3.v
.........\fe_fifo1.v
.........\fe_fifo2.v
.........\fe_generater_mode3by3.v
.........\Grads.v
.........\Gx_grad.v
.........\Gy_grad.v
sobel程序
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