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  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 5kb
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  • Author :zhaorongjian
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Introduction - If you have any usage issues, please Google them yourself
The whole system is divided into two modules: detection module and decoding module. Detection module of the completion of the serial sequence determine from the input A, B or C signal and the output pulse signs were pulse train Signal_A, Signal_B and Signal_C the same time, when the detection of either signal, BIT_EN_temp output a high pulse. Decoding module detection module according to the three flag pulses output 0/1 decoder, the output end of the Miller encoded data DOUT the same time, the output DATA_EN and BIT_EN two signs and signals.
Packet file list
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源代码\decode.v
......\decode_tb.v
......\miller_decode.v
......\miller_decode_tb.v
......\Signal_detect.v
......\Signal_detect_tb2.v
源代码
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