PCI interface sample program from lattice

PCI_Lattice\base_addr_chk.v
...........\config_mux.v
...........\config_mux.v.bak
...........\db\pcit32_verilog.asm.qmsg
...........\..\pcit32_verilog.asm_labs.ddb
...........\..\pcit32_verilog.cbx.xml
...........\..\pcit32_verilog.cmp.bpm
...........\..\pcit32_verilog.cmp.cdb
...........\..\pcit32_verilog.cmp.ecobp
...........\..\pcit32_verilog.cmp.hdb
...........\..\pcit32_verilog.cmp.logdb
...........\..\pcit32_verilog.cmp.rdb
...........\..\pcit32_verilog.cmp.tdb
...........\..\pcit32_verilog.cmp0.ddb
...........\..\pcit32_verilog.cmp2.ddb
...........\..\pcit32_verilog.db_info
...........\..\pcit32_verilog.eco.cdb
...........\..\pcit32_verilog.fit.qmsg
...........\..\pcit32_verilog.hier_info
...........\..\pcit32_verilog.hif
...........\..\pcit32_verilog.map.bpm
...........\..\pcit32_verilog.map.cdb
...........\..\pcit32_verilog.map.ecobp
...........\..\pcit32_verilog.map.hdb
...........\..\pcit32_verilog.map.logdb
...........\..\pcit32_verilog.map.qmsg
...........\..\pcit32_verilog.map_bb.cdb
...........\..\pcit32_verilog.map_bb.hdb
...........\..\pcit32_verilog.map_bb.hdbx
...........\..\pcit32_verilog.map_bb.logdb
...........\..\pcit32_verilog.pre_map.cdb
...........\..\pcit32_verilog.pre_map.hdb
...........\..\pcit32_verilog.psp
...........\..\pcit32_verilog.root_partition.cmp.atm
...........\..\pcit32_verilog.root_partition.cmp.dfp
...........\..\pcit32_verilog.root_partition.cmp.hdbx
...........\..\pcit32_verilog.root_partition.cmp.logdb
...........\..\pcit32_verilog.root_partition.cmp.rcf
...........\..\pcit32_verilog.root_partition.map.atm
...........\..\pcit32_verilog.root_partition.map.hdbx
...........\..\pcit32_verilog.root_partition.map.info
...........\..\pcit32_verilog.rtlv.hdb
...........\..\pcit32_verilog.rtlv_sg.cdb
...........\..\pcit32_verilog.rtlv_sg_swap.cdb
...........\..\pcit32_verilog.sgdiff.cdb
...........\..\pcit32_verilog.sgdiff.hdb
...........\..\pcit32_verilog.signalprobe.cdb
...........\..\pcit32_verilog.sld_design_entry.sci
...........\..\pcit32_verilog.sld_design_entry_dsc.sci
...........\..\pcit32_verilog.smp_dump.txt
...........\..\pcit32_verilog.syn_hier_info
...........\..\pcit32_verilog.tan.qmsg
...........\..\pcit32_verilog.tis_db_list.ddb
...........\..\pcit32_verilog.tmw_info
...........\..\pci_top.smp_dump.txt
...........\..\prev_cmp_pcit32_verilog.asm.qmsg
...........\..\prev_cmp_pcit32_verilog.fit.qmsg
...........\..\prev_cmp_pcit32_verilog.map.qmsg
...........\..\prev_cmp_pcit32_verilog.qmsg
...........\..\prev_cmp_pcit32_verilog.tan.qmsg
...........\..\prev_cmp_pci_top.qmsg
...........\glue.v
...........\pargen.v
...........\pcit32_verilog.asm.rpt
...........\pcit32_verilog.done
...........\pcit32_verilog.dpf
...........\pcit32_verilog.fit.rpt
...........\pcit32_verilog.fit.smsg
...........\pcit32_verilog.fit.summary
...........\pcit32_verilog.flow.rpt
...........\pcit32_verilog.map.rpt
...........\pcit32_verilog.map.smsg
...........\pcit32_verilog.map.summary
...........\pcit32_verilog.merge.rpt
...........\pcit32_verilog.pin
...........\pcit32_verilog.pof
...........\pcit32_verilog.qsf
...........\pcit32_verilog.qws
...........\pcit32_verilog.sof
...........\pcit32_verilog.sta.rpt
...........\pcit32_verilog.sta.summary
...........\pcit32_verilog.tan.rpt
...........\pcit32_verilog.tan.summary
...........\pcit32_verilog_assignment_defaults.qdf
...........\pcit32_verilog_description.txt
...........\pci_t32_top.xml
...........\pci_top.qpf
...........\pci_top.qws
...........\pci_top.v
...........\rd1008.pdf
...........\retry_count.v
...........\state_machine.v
...........\db
PCI_Lattice

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