DDR SDRAM Controller design

ddr sdram controller\ddr_sdram.pdf
....................\verilog
....................\.......\doc
....................\.......\...\ddr_sdram.pdf
....................\.......\model
....................\.......\.....\mt46v4m16.v
....................\.......\readme.txt
....................\.......\route
....................\.......\.....\ddr_sdram.csf
....................\.......\.....\ddr_sdram.esf
....................\.......\.....\ddr_sdram.psf
....................\.......\.....\ddr_sdram.quartus
....................\.......\.....\ddr_sdram.vqm
....................\.......\.....\pll1.v
....................\.......\simulation
....................\.......\..........\ddr_compile_all.v
....................\.......\..........\ddr_sdram_tb.v
....................\.......\..........\modelsim.ini
....................\.......\..........\readme.txt
....................\.......\..........\work
....................\.......\..........\....\altclklock
....................\.......\..........\....\..........\verilog.psm
....................\.......\..........\....\..........\_primary.dat
....................\.......\..........\....\..........\_primary.vhd
....................\.......\..........\....\ddr_command
....................\.......\..........\....\...........\verilog.psm
....................\.......\..........\....\...........\_primary.dat
....................\.......\..........\....\...........\_primary.vhd
....................\.......\..........\....\ddr_control_interface
....................\.......\..........\....\.....................\verilog.psm
....................\.......\..........\....\.....................\_primary.dat
....................\.......\..........\....\.....................\_primary.vhd
....................\.......\..........\....\ddr_data_path
....................\.......\..........\....\.............\verilog.psm
....................\.......\..........\....\.............\_primary.dat
....................\.......\..........\....\.............\_primary.vhd
....................\.......\..........\....\ddr_sdram
....................\.......\..........\....\.........\verilog.psm
....................\.......\..........\....\.........\_primary.dat
....................\.......\..........\....\.........\_primary.vhd
....................\.......\..........\....\ddr_sdram_tb
....................\.......\..........\....\............\verilog.psm
....................\.......\..........\....\............\_primary.dat
....................\.......\..........\....\............\_primary.vhd
....................\.......\..........\....\mt46v4m16
....................\.......\..........\....\.........\verilog.psm
....................\.......\..........\....\.........\_primary.dat
....................\.......\..........\....\.........\_primary.vhd
....................\.......\..........\....\pll1
....................\.......\..........\....\....\verilog.psm
....................\.......\..........\....\....\_primary.dat
....................\.......\..........\....\....\_primary.vhd
....................\.......\..........\....\_info
....................\.......\source
....................\.......\......\altclklock.v
....................\.......\......\ddr_Command.v
....................\.......\......\ddr_control_interface.v
....................\.......\......\ddr_data_path.v
....................\.......\......\ddr_sdram.v
....................\.......\......\Params.v
....................\.......\......\pll1.v
....................\.......\synthesis
....................\.......\.........\synplicity
....................\.......\.........\..........\ddr_data_path.srm
....................\.......\.........\..........\ddr_data_path.srr
....................\.......\.........\..........\ddr_data_path.srs
....................\.......\.........\..........\ddr_data_path.tlg
....................\.......\.........\..........\ddr_data_path.xrf
....................\.......\.........\..........\ddr_sdram.prj
....................\.......\.........\..........\ddr_sdram.sdc
....................\.......\.........\..........\ddr_sdram.srm
...............

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