using VHDL prepared by the two four binary-phase reduction, and the results will be there to rounding

Packet : 119128637sub4.rar filelist
sub4\LIB.DLS
sub4\sub4(1).cnf
sub4\sub4(2).cnf
sub4\sub4(3).cnf
sub4\sub4(4).cnf
sub4\sub4(5).cnf
sub4\sub4(6).cnf
sub4\sub4(7).cnf
sub4\sub4(8).cnf
sub4\sub4(9).cnf
sub4\sub4.acf
sub4\sub4.cnf
sub4\sub4.fit
sub4\sub4.hif
sub4\sub4.mmf
sub4\sub4.ndb
sub4\sub4.pin
sub4\sub4.pof
sub4\sub4.rpt
sub4\sub4.scf
sub4\sub4.snf
sub4\SUB4.sym
sub4\sub4.vhd
sub4\U3857185.DLS
sub4\U6614590.DLS
sub4\U8278438.DLS
sub4

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