modelsim works with verilog realized HDB3 coding, and testing procedures testbench

Packet : 9927414hdb3_verilog.rar filelist
hdb3\decode.v
hdb3\testbench.v
hdb3\testbench.v.bak
hdb3\work\_info
hdb3\work\testbench\_primary.vhd
hdb3\work\testbench\verilog.asm
hdb3\work\testbench\_primary.dat
hdb3\work\testbench
hdb3\work\decode\_primary.vhd
hdb3\work\decode\verilog.asm
hdb3\work\decode\_primary.dat
hdb3\work\decode
hdb3\work
hdb3\decode.v.bak
hdb3\hdb3.cr.mti
hdb3\hdb3.mpf
hdb3
hdb3\vsim.wlf

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