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fir_sine

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 18kb
  • Downloaded :0次
  • Author :jai
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
This implementation is moderately memory efficient because it stores only the first Pi/2 radians of sine values. The second Pi/2 radians is a mirror image of the first in time and the second Pi radians is a mirror image in amplitude of the first Pi radians. Memory could be saved if the increments were recorded rather than each absolute value. Fewer bits per value would be needed, however, extra hardware would be needed for an adder.
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fir_sine\fir.m
........\fir.vhd
........\sine.vhd
fir_sine
........\FIR FILTERS.doc
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