AAC' s idmct module, did not find verilog development environment, but this module is written in verilog.

imdct_dsp
.........\Blank512.hex
.........\bu.v
.........\cu.v
.........\finish_pulse.v
.........\flag.v
.........\hard_imag64.txt
.........\imdct.cr.mti
.........\imdct.mpf
.........\imdct.v
.........\imdct.v.bak
.........\imdct_bench.v
.........\imdct_bench.v.bak
.........\imdct_bench_tester.v
.........\imdct_dsp.v
.........\mu.v
.........\mux21.v
.........\mux21IR.v
.........\mux21IR.v.bak
.........\mux41.v
.........\OriSpecRom1024.hex
.........\OriSpecRom1024.qip
.........\OriSpecRom1024.v
.........\OriSpecRom1024.ver
.........\readme.txt
.........\send_spec.v
.........\SopRom512.hex
.........\SopRom512.qip
.........\SopRom512.v
.........\SopRom512.ver
.........\SopRom64.hex
.........\SopRom64.qip
.........\SopRom64.v
.........\SopRom64.ver
.........\sram512.v
.........\TfRom256.hex
.........\TfRom256.qip
.........\TfRom256.v
.........\TfRom256.ver
.........\TfRom32.hex
.........\TfRom32.qip
.........\TfRom32.v
.........\TfRom32.ver
.........\transcript
.........\vish_stacktrace.vstf
.........\vsim.wlf
.........\work
.........\....\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s
.........\....\..........................................\verilog.asm
.........\....\..........................................\_primary.dat
.........\....\..........................................\_primary.vhd
.........\....\@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n
.........\....\...............................................\verilog.asm
.........\....\...............................................\_primary.dat
.........\....\...............................................\_primary.vhd
.........\....\@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n
.........\....\...........................................................\verilog.asm
.........\....\...........................................................\_primary.dat
.........\....\...........................................................\_primary.vhd
.........\....\@m@f_cycloneiii_pll
.........\....\...................\verilog.asm
.........\....\...................\_primary.dat
.........\....\...................\_primary.vhd
.........\....\@m@f_pll_reg
.........\....\............\verilog.asm
.........\....\............\_primary.dat
.........\....\............\_primary.vhd
.........\....\@m@f_stratixiii_pll
.........\....\...................\verilog.asm
.........\....\...................\_primary.dat
.........\....\...................\_primary.vhd
.........\....\@m@f_stratixii_pll
.........\....\..................\verilog.asm
.........\....\..................\_primary.dat
.........\....\..................\_primary.vhd
.........\....\@m@f_stratix_pll
.........\....\................\verilog.asm
.........\....\................\_primary.dat
.........\....\................\_primary.vhd
.........\....\@ori@spec@rom1024
.........\....\.................\verilog.asm
.........\....\.................\_primary.dat
.........\....\.................\_primary.vhd
.........\....\@sop@rom512
.........\....\...........\verilog.asm
.........\....\...........\_primary.dat
.........\....\...........\_primary.vhd
.........\....\@sop@rom512_tester
.........\....\..................\verilog.asm
.........\....\..................\_primary.dat
.........\....\..................\_primary.vhd
.........\....\@sop@rom64
.........\....\..........\verilog.asm
.........\....\..........\_primary.dat
.........\....\..........\_primary.vhd
.........\....\@tf@rom256
.........\....\..........\verilog.asm
.........\....\..........\_primary.dat
.........\....\..........\_primary.vhd
.........\....\@tf@rom32

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