Written in VHDL language with the full-adder

f_adder\db\f_adder.cbx.xml
.......\..\f_adder.cmp.rdb
.......\..\f_adder.dbp
.......\..\f_adder.db_info
.......\..\f_adder.eco.cdb
.......\..\f_adder.hier_info
.......\..\f_adder.hif
.......\..\f_adder.map.cdb
.......\..\f_adder.map.hdb
.......\..\f_adder.map.logdb
.......\..\f_adder.map.qmsg
.......\..\f_adder.pre_map.cdb
.......\..\f_adder.pre_map.hdb
.......\..\f_adder.psp
.......\..\f_adder.pss
.......\..\f_adder.rtlv.hdb
.......\..\f_adder.rtlv_sg.cdb
.......\..\f_adder.rtlv_sg_swap.cdb
.......\..\f_adder.sgdiff.cdb
.......\..\f_adder.sgdiff.hdb
.......\..\f_adder.sld_design_entry.sci
.......\..\f_adder.sld_design_entry_dsc.sci
.......\..\f_adder.syn_hier_info
.......\..\f_adder.tis_db_list.ddb
.......\..\prev_cmp_f_adder.map.qmsg
.......\..\prev_cmp_f_adder.qmsg
.......\f_adder.done
.......\f_adder.flow.rpt
.......\f_adder.map.rpt
.......\f_adder.map.summary
.......\f_adder.qpf
.......\f_adder.qsf
.......\f_adder.qws
.......\f_adder.vhd
.......\f_adder.vhd.bak
.......\db
f_adder

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