Introduction - If you have any usage issues, please Google them yourself
usb1.1 verilog the source code. Simulation and test document, and now it is very difficult to find the paper test testbench
Packet : 75448191usb1_funct.rar filelist
usb1_funct\bench\verilog\tests.v
usb1_funct\bench\verilog\tests_lib.v
usb1_funct\bench\verilog\test_bench_top.v
usb1_funct\bench\verilog\timescale.v
usb1_funct\doc\README.txt
usb1_funct\doc\success_story.txt
usb1_funct\rtl\verilog\timescale.v
usb1_funct\rtl\verilog\usb1_core.v
usb1_funct\rtl\verilog\usb1_crc16.v
usb1_funct\rtl\verilog\usb1_crc5.v
usb1_funct\rtl\verilog\usb1_ctrl.v
usb1_funct\rtl\verilog\usb1_defines.v
usb1_funct\rtl\verilog\usb1_fifo2.v
usb1_funct\rtl\verilog\usb1_idma.v
usb1_funct\rtl\verilog\usb1_pa.v
usb1_funct\rtl\verilog\usb1_pd.v
usb1_funct\rtl\verilog\usb1_pe.v
usb1_funct\rtl\verilog\usb1_pl.v
usb1_funct\rtl\verilog\usb1_rom1.v
usb1_funct\rtl\verilog\usb1_utmi_if.v
usb1_funct\sim\rtl_sim\bin\Makefile
usb1_funct\sim\rtl_sim\run\Makefile
usb1_funct\sim\rtl_sim\run\waves\waves.do
usb1_funct\sim\rtl_sim\run\waves
usb1_funct\sim\rtl_sim\bin
usb1_funct\sim\rtl_sim\run
usb1_funct\bench\verilog
usb1_funct\rtl\verilog
usb1_funct\sim\rtl_sim
usb1_funct\bench
usb1_funct\doc
usb1_funct\rtl
usb1_funct\sim
usb1_funct