single bit half adder

halfadder\halfadder_xdb\tmp\ise\__OBJSTORE__\ProjectNavigatorGui\CViewSelector
.........\.............\...\...\............\...................\CViewSelector_StrTbl
.........\.............\...\...\............\................\dpm_project_main\dpm_project_main
.........\.............\...\...\............\................\................\dpm_project_main_StrTbl
.........\.............\...\...\............\................Gui\File-SynthesisOnly
.........\.............\...\...\............\...................\File-SynthesisOnly_StrTbl
.........\.............\...\...\............\xreport\Gc_RvReportViewer-Current-Module
.........\.............\...\...\............\.......\Gc_RvReportViewer-Current-Module_StrTbl
.........\.............\...\...\............\.......\Gc_RvReportViewer-Module-Data-halfadder
.........\.............\...\...\............\.......\Gc_RvReportViewer-Module-Data-halfadder_StrTbl
.........\.............\...\...\............\.......\Gc_RvReportViewer-Module-Data-Unknown
.........\.............\...\...\............\.......\Gc_RvReportViewer-Module-Data-Unknown_StrTbl
.........\.............\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default
.........\.............\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default_StrTbl
.........\.............\...\...\............\HierarchicalDesign\HDProject\HDProject
.........\.............\...\...\............\..................\.........\HDProject_StrTbl
.........\.............\...\...\............\ProjectNavigatorGui\Library-SynthesisOnly
.........\.............\...\...\............\...................\Library-SynthesisOnly_StrTbl
.........\.............\...\...\............\...................\Process-BehavioralSim-
.........\.............\...\...\............\...................\Process-BehavioralSim-DESUT_VHDL_ARCHITECTURE
.........\.............\...\...\............\...................\Process-BehavioralSim-DESUT_VHDL_ARCHITECTURE_StrTbl
.........\.............\...\...\............\...................\Process-BehavioralSim-_StrTbl
.........\.............\...\...\............\...................\Process-SynthesisOnly-
.........\.............\...\...\............\...................\Process-SynthesisOnly-DESUT_VHDL_ARCHITECTURE
.........\.............\...\...\............\...................\Process-SynthesisOnly-DESUT_VHDL_ARCHITECTURE_StrTbl
.........\.............\...\...\............\...................\Process-SynthesisOnly-_StrTbl
.........\.............\...\...\..REGISTRY__\fuse\regkeys
.........\.............\...\...\............\bitgen\regkeys
.........\.............\...\...\............\hprep6\regkeys
.........\.............\...\...\............\bitinit\regkeys
.........\.............\...\...\............\cpldfit\regkeys
.........\.............\...\...\............\dumpngdio\regkeys
.........\.............\...\...\............\XSLTProcess\regkeys
.........\.............\...\...\............\map\regkeys
.........\.............\...\...\............\par\regkeys
.........\.............\...\...\............\idem\regkeys
.........\.............\...\...\............\libgen\regkeys
.........\.............\...\...\............\netgen\regkeys
.........\.............\...\...\............\platgen\regkeys
.........\.............\...\...\............\ngc2edif\regkeys
.........\.............\...\...\............\...build\regkeys
.........\.............\...\...\............\..dbuild\regkeys
.........\.............\...\...\............\runner\regkeys
.........\.............\...\...\............\simgen\regkeys
.........\.............\...\...\............\xst\regkeys
.........\.............\...\...\............\trce\regkeys
.........\.............\...\...\............\.sim\regkeys
.........\.............\...\...\............\xpwr\regkeys
.........\.............\...\...\............\vhpcomp\regkeys
.........\.............\...\...\............\taengine\regkeys
.........\.............\...\...\............\vlogcomp\regkeys
.........\.............\...\...\............\common\regkeys
.........\.............\...\...\............\Proje

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