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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 4kb
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  • Author :chencong
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Introduction - If you have any usage issues, please Google them yourself
Dozens of classic procedure, the structure described in the four-level with full-adder, a full-adder, using the conditional operator described in the four selected 1 MUX, etc.
Packet file list
(Preview for download)
add4_1.v
add4_2.v
add4_3.v
count4.v
full_add1.v
full_add2.v
full_add3.v
full_add4.v
full_add5.v
half_add1.v
half_add2.v
half_add3.v
half_add4.v
mux2_1a.v
mux2_1b.v
mux2_1c.v
mux4_1a.v
mux4_1b.v
mux4_1c.v
mux4_1d.v
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