The use of Altera' s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 development board with hardware description language to achieve a ROM memory.

rom
...\db
...\..\mux_1hc.tdf
...\..\prev_cmp_rom.asm.qmsg
...\..\prev_cmp_rom.fit.qmsg
...\..\prev_cmp_rom.map.qmsg
...\..\prev_cmp_rom.qmsg
...\..\prev_cmp_rom.sim.qmsg
...\..\prev_cmp_rom.tan.qmsg
...\..\ram0_rom_1d582.hdl.mif
...\..\rom.asm.qmsg
...\..\rom.cbx.xml
...\..\rom.cmp.bpm
...\..\rom.cmp.cdb
...\..\rom.cmp.ecobp
...\..\rom.cmp.hdb
...\..\rom.cmp.logdb
...\..\rom.cmp.rdb
...\..\rom.cmp.tdb
...\..\rom.cmp0.ddb
...\..\rom.cmp_bb.cdb
...\..\rom.cmp_bb.hdb
...\..\rom.cmp_bb.logdb
...\..\rom.cmp_bb.rcf
...\..\rom.dbp
...\..\rom.db_info
...\..\rom.eco.cdb
...\..\rom.eds_overflow
...\..\rom.fit.qmsg
...\..\rom.fnsim.hdb
...\..\rom.fnsim.qmsg
...\..\rom.hier_info
...\..\rom.hif
...\..\rom.map.bpm
...\..\rom.map.cdb
...\..\rom.map.ecobp
...\..\rom.map.hdb
...\..\rom.map.logdb
...\..\rom.map.qmsg
...\..\rom.map_bb.cdb
...\..\rom.map_bb.hdb
...\..\rom.map_bb.logdb
...\..\rom.pre_map.cdb
...\..\rom.pre_map.hdb
...\..\rom.psp
...\..\rom.pss
...\..\rom.rtlv.hdb
...\..\rom.rtlv_sg.cdb
...\..\rom.rtlv_sg_swap.cdb
...\..\rom.sgdiff.cdb
...\..\rom.sgdiff.hdb
...\..\rom.signalprobe.cdb
...\..\rom.sim.cvwf
...\..\rom.sim.hdb
...\..\rom.sim.qmsg
...\..\rom.sim.rdb
...\..\rom.simfam
...\..\rom.sld_design_entry.sci
...\..\rom.sld_design_entry_dsc.sci
...\..\rom.syn_hier_info
...\..\rom.tan.qmsg
...\..\rom.tis_db_list.ddb
...\..\wed.wsf
...\rom.asm.rpt
...\rom.done
...\rom.fit.rpt
...\rom.fit.smsg
...\rom.fit.summary
...\rom.flow.rpt
...\rom.map.rpt
...\rom.map.summary
...\rom.pin
...\rom.pof
...\rom.qpf
...\rom.qsf
...\rom.qws
...\rom.sim.rpt
...\rom.sof
...\rom.tan.rpt
...\rom.tan.summary
...\rom.vhd
...\rom.vhd.bak
...\rom.vwf

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