The use of Altera' s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 Development Board to achieve FIFO queue.

fifo
....\db
....\..\add_sub_3rh.tdf
....\..\fifo.cbx.xml
....\..\fifo.cmp.rdb
....\..\fifo.dbp
....\..\fifo.db_info
....\..\fifo.eco.cdb
....\..\fifo.eds_overflow
....\..\fifo.fnsim.cdb
....\..\fifo.fnsim.hdb
....\..\fifo.fnsim.qmsg
....\..\fifo.hier_info
....\..\fifo.hif
....\..\fifo.map.bpm
....\..\fifo.map.cdb
....\..\fifo.map.ecobp
....\..\fifo.map.hdb
....\..\fifo.map.logdb
....\..\fifo.map.qmsg
....\..\fifo.map_bb.cdb
....\..\fifo.map_bb.hdb
....\..\fifo.map_bb.logdb
....\..\fifo.pre_map.cdb
....\..\fifo.pre_map.hdb
....\..\fifo.psp
....\..\fifo.pss
....\..\fifo.rtlv.hdb
....\..\fifo.rtlv_sg.cdb
....\..\fifo.rtlv_sg_swap.cdb
....\..\fifo.sgdiff.cdb
....\..\fifo.sgdiff.hdb
....\..\fifo.sim.cvwf
....\..\fifo.sim.hdb
....\..\fifo.sim.qmsg
....\..\fifo.sim.rdb
....\..\fifo.simfam
....\..\fifo.sld_design_entry.sci
....\..\fifo.sld_design_entry_dsc.sci
....\..\fifo.syn_hier_info
....\..\fifo.tis_db_list.ddb
....\..\mux_hfc.tdf
....\..\prev_cmp_fifo.map.qmsg
....\..\prev_cmp_fifo.qmsg
....\..\wed.wsf
....\fifo.done
....\fifo.flow.rpt
....\fifo.map.rpt
....\fifo.map.summary
....\fifo.qpf
....\fifo.qsf
....\fifo.qws
....\fifo.sim.rpt
....\fifo.vhd
....\fifo.vhd.bak
....\fifo.vwf

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