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  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2012-11-26
  • Size : 5.2mb
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  • Author :sudhir
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
SPI Verilog code with programmable clock
Packet file list
(Preview for download)
spi
...\branches
...\tags
...\....\asyst_2
...\....\.......\rtl
...\....\.......\...\verilog
...\....\.......\...\.......\spi_clgen.v
...\....\.......\...\.......\spi_defines.v
...\....\.......\...\.......\spi_shift.v
...\....\.......\...\.......\spi_top.v
...\....\.......\...\.......\timescale.v
...\....\asyst_3
...\....\.......\rtl
...\....\.......\...\verilog
...\....\.......\...\.......\spi_clgen.v
...\....\.......\...\.......\spi_defines.v
...\....\.......\...\.......\spi_shift.v
...\....\.......\...\.......\spi_top.v
...\....\.......\...\.......\timescale.v
...\....\initial
...\....\.......\bench
...\....\.......\.....\verilog
...\....\.......\.....\.......\spi_slave_model.v
...\....\.......\.....\.......\tb_spi_top.v
...\....\.......\.....\.......\wb_master_model.v
...\....\.......\doc
...\....\.......\...\src
...\....\.......\...\...\spi.doc
...\....\.......\rtl
...\....\.......\...\verilog
...\....\.......\...\.......\spi_clgen.v
...\....\.......\...\.......\spi_defines.v
...\....\.......\...\.......\spi_shift.v
...\....\.......\...\.......\spi_top.v
...\....\.......\...\.......\timescale.v
...\....\.......\sim
...\....\.......\...\run
...\....\.......\...\...\sim
...\....\.......\...\...\tcl.scr
...\....\rel_1
...\....\.....\bench
...\....\.....\.....\verilog
...\....\.....\.....\.......\spi_slave_model.v
...\....\.....\.....\.......\tb_spi_top.v
...\....\.....\.....\.......\wb_master_model.v
...\....\.....\doc
...\....\.....\...\spi.pdf
...\....\.....\...\src
...\....\.....\...\...\spi.doc
...\....\.....\rtl
...\....\.....\...\verilog
...\....\.....\...\.......\spi_clgen.v
...\....\.....\...\.......\spi_defines.v
...\....\.....\...\.......\spi_shift.v
...\....\.....\...\.......\spi_top.v
...\....\.....\...\.......\timescale.v
...\....\.....\sim
...\....\.....\...\run
...\....\.....\...\...\sim
...\....\.....\...\...\tcl.scr
...\....\rel_2
...\....\.....\bench
...\....\.....\.....\verilog
...\....\.....\.....\.......\spi_slave_model.v
...\....\.....\.....\.......\tb_spi_top.v
...\....\.....\.....\.......\wb_master_model.v
...\....\.....\doc
...\....\.....\...\spi.pdf
...\....\.....\...\src
...\....\.....\...\...\spi.doc
...\....\.....\rtl
...\....\.....\...\verilog
...\....\.....\...\.......\spi_clgen.v
...\....\.....\...\.......\spi_defines.v
...\....\.....\...\.......\spi_shift.v
...\....\.....\...\.......\spi_top.v
...\....\.....\...\.......\timescale.v
...\....\.....\sim
...\....\.....\...\run
...\....\.....\...\...\sim
...\....\.....\...\...\tcl.scr
...\....\rel_3
...\....\.....\bench
...\....\.....\.....\verilog
...\....\.....\.....\.......\spi_slave_model.v
...\....\.....\.....\.......\tb_spi_top.v
...\....\.....\.....\.......\wb_master_model.v
...\....\.....\doc
...\....\.....\...\spi.pdf
...\....\.....\...\src
...\....\.....\...\...\spi.doc
...\....\.....\rtl
...\....\.....\...\verilog
...\....\.....\...\.......\spi_clgen.v
...\....\.....\...\.......\spi_defines.v
...\....\.....\...\.......\spi_shift.v
...\....\.....\...\.......\spi_top.v
...\....\.....\...\.......\timescale.v
...\....\.....\sim
...\....\.....\...\run
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