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VHDL-FPGA-Verilog
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Update : 2012-11-26
Size : 3kb
Downloaded :0次
Author :
culun
About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
Reedit
Complete FIFO full source code, through the simulation of the complete FIFO full source code, through the simulation of
Packet file list
(Preview for download)
可综合的FIFO
............\使用说明请参看右侧注释====〉〉.txt
............\可综合的FIFO.v
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