Verilog HDL prepared with 16* 2 LCD display one world, one dream. Compression package, including all documents, use the chips for EP2C5T144, download final test.

LCD1
....\1.bdf
....\db
....\..\LCD.asm.qmsg
....\..\LCD.asm_labs.ddb
....\..\LCD.cbx.xml
....\..\LCD.cmp.bpm
....\..\LCD.cmp.cdb
....\..\LCD.cmp.ecobp
....\..\LCD.cmp.hdb
....\..\LCD.cmp.logdb
....\..\LCD.cmp.rdb
....\..\LCD.cmp.tdb
....\..\LCD.cmp0.ddb
....\..\LCD.cmp_bb.cdb
....\..\LCD.cmp_bb.hdb
....\..\LCD.cmp_bb.logdb
....\..\LCD.cmp_bb.rcf
....\..\LCD.dbp
....\..\LCD.db_info
....\..\LCD.eco.cdb
....\..\LCD.fit.qmsg
....\..\LCD.hier_info
....\..\LCD.hif
....\..\LCD.map.bpm
....\..\LCD.map.cdb
....\..\LCD.map.ecobp
....\..\LCD.map.hdb
....\..\LCD.map.logdb
....\..\LCD.map.qmsg
....\..\LCD.map_bb.cdb
....\..\LCD.map_bb.hdb
....\..\LCD.map_bb.logdb
....\..\LCD.pre_map.cdb
....\..\LCD.pre_map.hdb
....\..\LCD.psp
....\..\LCD.pss
....\..\LCD.rtlv.hdb
....\..\LCD.rtlv_sg.cdb
....\..\LCD.rtlv_sg_swap.cdb
....\..\LCD.sgdiff.cdb
....\..\LCD.sgdiff.hdb
....\..\LCD.signalprobe.cdb
....\..\LCD.sld_design_entry.sci
....\..\LCD.sld_design_entry_dsc.sci
....\..\LCD.smp_dump.txt
....\..\LCD.syn_hier_info
....\..\LCD.tan.qmsg
....\..\LCD.tis_db_list.ddb
....\..\prev_cmp_LCD.asm.qmsg
....\..\prev_cmp_LCD.fit.qmsg
....\..\prev_cmp_LCD.map.qmsg
....\..\prev_cmp_LCD.qmsg
....\..\prev_cmp_LCD.tan.qmsg
....\LCD.asm.rpt
....\lcd.bsf
....\LCD.done
....\LCD.dpf
....\LCD.fit.rpt
....\LCD.fit.smsg
....\LCD.fit.summary
....\LCD.flow.rpt
....\LCD.map.rpt
....\LCD.map.summary
....\LCD.pin
....\LCD.pof
....\LCD.qpf
....\LCD.qsf
....\LCD.qws
....\LCD.sof
....\LCD.tan.rpt
....\LCD.tan.summary
....\lcd.v
....\lcd.v.bak

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