Xilinx embeded system labs

labs
....\ecs_lab
....\.......\count_1.asy
....\.......\count_1.ngc
....\.......\count_1.sym
....\.......\count_1.v
....\.......\count_1.veo
....\.......\count_1.vhd
....\.......\count_1.vho
....\.......\count_1.xco
....\.......\count_1_flist.txt
....\.......\count_1_readme.txt
....\.......\count_1_xmdf.tcl
....\.......\designA.jhd
....\.......\designA.sch
....\.......\designA.schlog
....\.......\designA_summary.html
....\.......\ecs_lab.ise
....\.......\ecs_lab.ise_ISE_Backup
....\.......\ecs_lab.restore
....\.......\ST.DIA
....\.......\stateCadApp.cmd
....\.......\templates
....\.......\.........\coregen.xml
....\.......\tmp
....\.......\...\_cg
....\.......\_xmsgs
....\hdlsynth
....\........\am2910.v
....\........\control.v
....\........\regcnt.v
....\........\stack.v
....\........\upc.v
....\........\y.v
....\isim
....\....\automake.log
....\....\DETECTOR.DIA
....\....\DETECTOR.vhd
....\....\lab.dhp
....\....\lab.ise
....\....\lab.ise.old
....\....\lab.ise_ISE_Backup
....\....\lab_ise7_bak.zip
....\....\lab_ise9migration.zip
....\....\prjname.lso
....\....\top.lso
....\....\top.prj
....\....\top.stx
....\....\top.vhd
....\....\top_summary.html
....\....\top_vhdl.prj
....\....\userlang.tpl
....\....\_import.dmo
....\....\_xmsgs
....\....\__projnav.log
....\synthoptions
....\............\am2910.v
....\............\AM2910_summary.html
....\............\automake.log
....\............\control.v
....\............\coregen.log
....\............\coregen.prj
....\............\lab2.dhp
....\............\lab2.ise
....\............\lab2.ise.old
....\............\lab2.ise_ISE_Backup
....\............\lab2.jid
....\............\lab2.restore
....\............\lab2_ise7_bak.zip
....\............\lab2_ise9migration.zip
....\............\regcnt.v
....\............\stack.v
....\............\upc.v
....\............\y.v
....\............\_xmsgs
....\............\__projnav.log

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