ALU modeling verilog codes and testbench

ADS
...\ahb_slave_include.v
...\arm_top.bdf
...\pld_slave.bdf
...\pld_slave.BSF
...\simulation
...\..........\modelsim
...\..........\........\bfm_wave.do
...\..........\........\edit_mpf.txt
...\..........\........\fullmodel_wave.do
...\..........\........\input.dat
...\..........\........\run_rtl_bfm_sim.do
...\..........\........\run_timing_bfm_sim.do
...\..........\........\slavememory.cfg.dat
...\software
...\........\alu_demo.c
...\........\armc_startup.S
...\........\int_ctrl00.h
...\........\irq.c
...\........\retarget.c
...\........\tutorial_code.s
...\........\uart00.h
...\........\uartcomm.c
...\........\uartcomm.h
GNU
...\ahb_slave_include.v
...\arm_top.bdf
...\pld_slave.bdf
...\pld_slave.BSF
...\simulation
...\..........\modelsim
...\..........\........\bfm_wave.do
...\..........\........\edit_mpf.txt
...\..........\........\fullmodel_wave.do
...\..........\........\input.dat
...\..........\........\run_rtl_bfm_sim.do
...\..........\........\run_timing_bfm_sim.do
...\..........\........\slavememory.cfg.dat
...\software
...\........\tutorial_code.s
rtl
...\ahb_slave_include.v
...\ahb_slave_sm.v
...\alu.v
...\pld_slave.v
...\regfile.v
testbench
.........\arm_top_tb.v
ug_arm_hardware_design-v1.5.pdf

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