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modelsim

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 132kb
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  • Author :chang
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
Modelsim simulation study and an excellent example of a script
Packet file list
(Preview for download)
学习modelsim_脚本仿真的绝佳范例
...............................\使用说明请参看右侧注释====〉〉.txt
...............................\学习modelsim 脚本仿真的绝佳范例
...............................\...............................\fifo
...............................\...............................\....\c
...............................\...............................\....\doc
...............................\...............................\....\...\design
...............................\...............................\....\...\......\AHB_ARBITER.doc
...............................\...............................\....\...\......\AHB_MASTER.doc
...............................\...............................\....\...\verification
...............................\...............................\....\sim
...............................\...............................\....\...\ModelSim
...............................\...............................\....\...\........\scripts
...............................\...............................\....\...\........\.......\run.f
...............................\...............................\....\...\........\.......\signal.f
...............................\...............................\....\...\........\.......\sim.do
...............................\...............................\....\...\........\.......\transcript
...............................\...............................\....\...\........\sim.bat
...............................\...............................\....\...\........\work
...............................\...............................\....\...\........\....\vsim.wlf
...............................\...............................\....\...\........\....\work
...............................\...............................\....\...\........\....\....\_info
...............................\...............................\....\...\vcs
...............................\...............................\....\src
...............................\...............................\....\...\Verilog
...............................\...............................\....\...\.......\fifo.v
...............................\...............................\....\...\vhdl
...............................\...............................\....\syn
...............................\...............................\....\...\ise
...............................\...............................\....\...\synopsys
...............................\...............................\....\...\........\atc18cond.dcsh
...............................\...............................\....\...\........\atc25cond.dcsh
...............................\...............................\....\...\........\atc25setup.dcsh
...............................\...............................\....\...\........\atc35setup.dcsh
...............................\...............................\....\...\........\fs90cond.dcsh
...............................\...............................\....\...\........\fs90setup.dcsh
...............................\...............................\....\...\........\leon.dcsh
...............................\...............................\....\...\........\leon.fc2
...............................\...............................\....\...\........\leon_eth.dcsh
...............................\...............................\....\...\........\leon_eth_pci.dcsh
...............................\...............................\....\...\........\leon_pci.dcsh
...............................\...............................\....\...\........\Makefile
...............................\...............................\....\...\........\readme
...............................\...............................\....\...\........\work
...............................\...............................\....\...\synplify
...............................\...............................\....\...\........\ethermac.v
...............................\...............................\....\...\........\leon.prj
...............................\..........
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