Turbo Decoder Release 0.3* Double binary, DVB-RCS code* Soft Output Viterbi Algorithm* M yHDL cycle/bit accurate model* Synthesizable VHDL model

Packet : 9927450turbo_vhdl.rar filelist
turbo[1]
turbo[1]\makeDist
turbo[1]\src
turbo[1]\src\vhdl
turbo[1]\src\vhdl\abPermut_e.vhd
turbo[1]\src\vhdl\abPermut_synth.vhd
turbo[1]\src\vhdl\accDistSel_e.vhd
turbo[1]\src\vhdl\accDistSel_synth.vhd
turbo[1]\src\vhdl\accDist_e.vhd
turbo[1]\src\vhdl\accDist_synth.vhd
turbo[1]\src\vhdl\acs_e.vhd
turbo[1]\src\vhdl\acs_synth.vhd
turbo[1]\src\vhdl\adder_e.vhd
turbo[1]\src\vhdl\adder_synth.vhd
turbo[1]\src\vhdl\clkDiv_e.vhd
turbo[1]\src\vhdl\clkDiv_synth.vhd
turbo[1]\src\vhdl\clkrst_beh.vhd
turbo[1]\src\vhdl\clkrst_e.vhd
turbo[1]\src\vhdl\cmp2_e.vhd
turbo[1]\src\vhdl\cmp2_synth.vhd
turbo[1]\src\vhdl\cod2_e.vhd
turbo[1]\src\vhdl\cod2_synth.vhd
turbo[1]\src\vhdl\cod3_e.vhd
turbo[1]\src\vhdl\cod3_synth.vhd
turbo[1]\src\vhdl\coder_e.vhd
turbo[1]\src\vhdl\coder_synth.vhd
turbo[1]\src\vhdl\delayer_e.vhd
turbo[1]\src\vhdl\delayer_synth.vhd
turbo[1]\src\vhdl\distances_e.vhd
turbo[1]\src\vhdl\distances_synth.vhd
turbo[1]\src\vhdl\distance_e.vhd
turbo[1]\src\vhdl\distance_synth.vhd
turbo[1]\src\vhdl\extInf_e.vhd
turbo[1]\src\vhdl\extInf_synth.vhd
turbo[1]\src\vhdl\interleaver_e.vhd
turbo[1]\src\vhdl\interleaver_synth.vhd
turbo[1]\src\vhdl\iteration_e.vhd
turbo[1]\src\vhdl\iteration_synth.vhd
turbo[1]\src\vhdl\limiter_e.vhd
turbo[1]\src\vhdl\limiter_synth.vhd
turbo[1]\src\vhdl\min4_e.vhd
turbo[1]\src\vhdl\min4_synth.vhd
turbo[1]\src\vhdl\min8_e.vhd
turbo[1]\src\vhdl\min8_synth.vhd
turbo[1]\src\vhdl\mux2_e.vhd
turbo[1]\src\vhdl\mux2_synth.vhd
turbo[1]\src\vhdl\mux4_e.vhd
turbo[1]\src\vhdl\mux4_synth.vhd
turbo[1]\src\vhdl\mux8_e.vhd
turbo[1]\src\vhdl\mux8_synth.vhd
turbo[1]\src\vhdl\opposite_e.vhd
turbo[1]\src\vhdl\opposite_synth.vhd
turbo[1]\src\vhdl\partDistance_e.vhd
turbo[1]\src\vhdl\partDistance_synth.vhd
turbo[1]\src\vhdl\punct_e.vhd
turbo[1]\src\vhdl\punct_synth.vhd
turbo[1]\src\vhdl\reduction_e.vhd
turbo[1]\src\vhdl\reduction_synth.vhd
turbo[1]\src\vhdl\reg_e.vhd
turbo[1]\src\vhdl\reg_synth.vhd
turbo[1]\src\vhdl\sova_e.vhd
turbo[1]\src\vhdl\sova_synth.vhd
turbo[1]\src\vhdl\stateSel_e.vhd
turbo[1]\src\vhdl\stateSel_synth.vhd
turbo[1]\src\vhdl\subs_e.vhd
turbo[1]\src\vhdl\subs_synth.vhd
turbo[1]\src\vhdl\trellis1_e.vhd
turbo[1]\src\vhdl\trellis1_synth.vhd
turbo[1]\src\vhdl\trellis2_e.vhd
turbo[1]\src\vhdl\trellis2_synth.vhd
turbo[1]\src\vhdl\turboDec_e.vhd
turbo[1]\src\vhdl\turboDec_synth.vhd
turbo[1]\src\vhdl\turbopack.vhd
turbo[1]\src\vhdl\zPermut_e.vhd
turbo[1]\src\vhdl\zPermut_synth.vhd
turbo[1]\src\myhdl
turbo[1]\src\myhdl\acs.py
turbo[1]\src\myhdl\args.py
turbo[1]\src\myhdl\clock.py
turbo[1]\src\myhdl\coder.py
turbo[1]\src\myhdl\distances.py
turbo[1]\src\myhdl\extInf.py
turbo[1]\src\myhdl\interleaver.py
turbo[1]\src\myhdl\iteration.py
turbo[1]\src\myhdl\launchTurbo.py
turbo[1]\src\myhdl\limiter.py
turbo[1]\src\myhdl\misc.py
turbo[1]\src\myhdl\noiser.py
turbo[1]\src\myhdl\permut.py
turbo[1]\src\myhdl\punct.py
turbo[1]\src\myhdl\select.py
turbo[1]\src\myhdl\sova.py
turbo[1]\src\myhdl\synthesis.py
turbo[1]\src\myhdl\testbench.py
turbo[1]\src\myhdl\trellis.py
turbo[1]\src\myhdl\turboTop.py
turbo[1]\doc
turbo[1]\doc\LICENSE.txt
turbo[1]\doc\README.txt
turbo[1]\doc\turbo.pdf

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