The LatticeMico8™ is an 8-bit microcontroller optimized for Field Programmable Gate Arrays (FPGAs) and Crossover Programmable Logic Device architectures from Lattice. Combining a full 18-bit wide instruction set with 16 or 32 General Purpose registers, the LatticeMico8 is a flexible Verilog and VHDL reference design suitable for a wide variety of markets, including communications, consumer, computer, medical, industrial, and automotive. The core consumes minimal device resources, less than 200 Look Up Tables (LUTs) in the smallest configuration, while maintaining a broad feature set.

LatticeMico8_V3_0_Verilog
.........................\models
.........................\......\pmi
.........................\......\...\pmi_add.v
.........................\......\...\pmi_addsub.v
.........................\......\...\pmi_complex_mult.v
.........................\......\...\pmi_constant_mult.v
.........................\......\...\pmi_counter.v
.........................\......\...\pmi_def.v
.........................\......\...\pmi_distributed_dpram.v
.........................\......\...\pmi_distributed_rom.v
.........................\......\...\pmi_distributed_shift_reg.v
.........................\......\...\pmi_distributed_spram.v
.........................\......\...\pmi_dsp_mac.v
.........................\......\...\pmi_dsp_mult.v
.........................\......\...\pmi_dsp_multaddsub.v
.........................\......\...\pmi_dsp_multaddsubsum.v
.........................\......\...\pmi_fifo.v
.........................\......\...\pmi_fifo_dc.v
.........................\......\...\pmi_mac.v
.........................\......\...\pmi_mult.v
.........................\......\...\pmi_multaddsub.v
.........................\......\...\pmi_multaddsubsum.v
.........................\......\...\pmi_pll.v
.........................\......\...\pmi_ram_dp.v
.........................\......\...\pmi_ram_dp_true.v
.........................\......\...\pmi_ram_dq.v
.........................\......\...\pmi_rom.v
.........................\......\...\pmi_sub.v
.........................\......\xo
.........................\......\..\sim
.........................\......\..\...\AGEB2.v
.........................\......\..\...\ALEB2.v
.........................\......\..\...\AND2.v
.........................\......\..\...\AND3.v
.........................\......\..\...\AND4.v
.........................\......\..\...\AND5.v
.........................\......\..\...\ANEB2.v
.........................\......\..\...\BB.v
.........................\......\..\...\BBPD.v
.........................\......\..\...\BBPU.v
.........................\......\..\...\BBW.v
.........................\......\..\...\BUFBA.v
.........................\......\..\...\CB2.v
.........................\......\..\...\CCU2.v
.........................\......\..\...\CD2.v
.........................\......\..\...\CU2.v
.........................\......\..\...\DP8KB.v
.........................\......\..\...\DPR16X2B.v
.........................\......\..\...\EHXPLLC.v
.........................\......\..\...\FADD2.v
.........................\......\..\...\FADSU2.v
.........................\......\..\...\FD1P3AX.v
.........................\......\..\...\FD1P3AY.v
.........................\......\..\...\FD1P3BX.v
.........................\......\..\...\FD1P3DX.v
.........................\......\..\...\FD1P3IX.v
.........................\......\..\...\FD1P3JX.v
.........................\......\..\...\FD1S1A.v
.........................\......\..\...\FD1S1AY.v
.........................\......\..\...\FD1S1B.v
.........................\......\..\...\FD1S1D.v
.........................\......\..\...\FD1S1I.v
.........................\......\..\...\FD1S1J.v
.........................\......\..\...\FD1S3AX.v
.........................\......\..\...\FD1S3AY.v
.........................\......\..\...\FD1S3BX.v
.........................\......\..\...\FD1S3DX.v
.........................\......\..\...\FD1S3IX.v
.........................\......\..\...\FD1S3JX.v
.........................\......\..\...\FIFO8KA.v
.........................\......\..\...\FL1P3AY.v
.........................\......\..\...\FL1P3AY_FUNC.v
.........................\......\..\...\FL1P3AZ.v
.........................\......\..\...\FL1P3AZ_FUNC.v
.........................\......\..\...\FL1P3BX.v
.........................\......\..\...\FL1P3BX_FUNC.v
.........................\......\..\...\FL1P3DX.v
.........................\......\..\...\FL1P3DX_FUNC.v
.........................\......\..\...\FL1P3IY.v
.........................\......\..\...\FL1P3IY_FUNC.v
.........................\......\..\...\FL1P3JY.v
.........................\.....

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