VHDL Design of BCD to 7-segment decoder using PROM

7-segment
.........\.untf
.........\7-segment.dhp
.........\7-segment.npl
.........\automake.log
.........\bitgen.ut
.........\coregen.log
.........\coregen.prj
.........\coregen_lock
.........\ex3.bgn
.........\ex3.bit
.........\ex3.bld
.........\ex3.cmd_log
.........\ex3.drc
.........\ex3.lfp
.........\ex3.lso
.........\ex3.mrp
.........\ex3.nc1
.........\ex3.ncd
.........\ex3.ngc
.........\ex3.ngd
.........\ex3.ngm
.........\ex3.ngr
.........\ex3.pad
.........\ex3.pad_txt
.........\ex3.par
.........\ex3.pcf
.........\ex3.placed_ncd_tracker
.........\ex3.prj
.........\ex3.routed_ncd_tracker
.........\ex3.stx
.........\ex3.syr
.........\ex3.twr
.........\ex3.twx
.........\ex3.ucf
.........\ex3.ucf.untf
.........\ex3.ut
.........\ex3.vhdl
.........\ex3.xpi
.........\ex3_map.ncd
.........\ex3_map.ngm
.........\ex3_pad.csv
.........\ex3_pad.txt
.........\prjname.lso
.........\xst
.........\...\work
.........\...\....\hdllib.ref
.........\...\....\hdpdeps.ref
.........\...\....\sub00
.........\...\....\.....\vhpl00.vho
.........\...\....\.....\vhpl01.vho
.........\_impact.cmd
.........\_impact.log
.........\_ngo
.........\....\netlist.lst
.........\_pace.ucf
.........\_tmp_
.........\.....\_ctd
.........\__projnav
.........\.........\7-segment.gfl
.........\.........\7-segment_flowplus.gfl
.........\.........\bitgen.rsp
.........\.........\coregen.rsp
.........\.........\ednTOngd_tcl.rsp
.........\.........\ex3.xst
.........\.........\ex3_ncdTOut_tcl.rsp
.........\.........\map.log
.........\.........\nc1TOncd_tcl.rsp
.........\.........\par.log
.........\.........\parentAssignPackagePinsApp_tcl.rsp
.........\.........\posttrc.log
.........\.........\runXst_tcl.rsp
.........\.........\xst_sprjTOstx_tcl.rsp
.........\__projnav.log

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