a 4-bit shift register which is active on the rising edge of the clock. The register should be able to shift left, shift right, accept a serial and parallel (load) input, and have an asynchronous preset (“1111”) and clear(“0000”) capability.

T3_1
....\automake.log
....\pepExtractor.prj
....\prjname.lso
....\T3_1.dhp
....\T3_1.npl
....\testwave.ado
....\testwave.ano
....\testwave.ANT
....\testwave.tbw
....\testwave.vhw
....\transcript
....\upcount.cmd_log
....\upcount.lso
....\upcount.ngr
....\upcount.prj
....\upcount.stx
....\upcount.syr
....\upcount.vhd
....\work
....\....\testwave
....\....\........\testbench_arch.dat
....\....\........\testbench_arch.psm
....\....\........\_primary.dat
....\....\upcount
....\....\.......\behavioral.dat
....\....\.......\behavioral.psm
....\....\.......\_primary.dat
....\....\upcount_cfg
....\....\...........\_primary.dat
....\....\...........\_vhdl.psm
....\....\_info
....\xst
....\...\work
....\...\....\hdllib.ref
....\...\....\hdpdeps.ref
....\...\....\sub00
....\...\....\.....\vhpl00.vho
....\...\....\.....\vhpl01.vho
....\__projnav
....\.........\coregen.rsp
....\.........\hb_cmds
....\.........\runXst_tcl.rsp
....\.........\T3_1.gfl
....\.........\T3_1_flowplus.gfl
....\.........\upcount.xst
....\.........\xst_sprjTOstx_tcl.rsp
....\__projnav.log

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