State machine used for A/D converter sampling control circuit 0809 is achieved. Tools: Quartus ii 6.0 Language: VHDL

ADC0809
.......\adcint.done
.......\adcint.flow.rpt
.......\adcint.map.rpt
.......\adcint.map.summary
.......\adcint.qpf
.......\adcint.qsf
.......\adcint.qws
.......\adcint.vhd
.......\db
.......\..\adcint.cbx.xml
.......\..\adcint.cmp.rdb
.......\..\adcint.dbp
.......\..\adcint.db_info
.......\..\adcint.eco.cdb
.......\..\adcint.hier_info
.......\..\adcint.hif
.......\..\adcint.map.cdb
.......\..\adcint.map.hdb
.......\..\adcint.map.logdb
.......\..\adcint.map.qmsg
.......\..\adcint.pre_map.cdb
.......\..\adcint.pre_map.hdb
.......\..\adcint.psp
.......\..\adcint.rtlv.hdb
.......\..\adcint.rtlv_sg.cdb
.......\..\adcint.rtlv_sg_swap.cdb
.......\..\adcint.sgdiff.cdb
.......\..\adcint.sgdiff.hdb
.......\..\adcint.sld_design_entry.sci
.......\..\adcint.sld_design_entry_dsc.sci
.......\..\adcint.smp_dump.txt
.......\..\adcint.syn_hier_info

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