This is an FPGA-based SDRAM controller system, the read and write operations to SDRAM to achieve the control of timing

实战训练13 SDRAM读写控制的实现与Modelsim仿真
............................................\doc
............................................\...\micron_sdram.pdf
............................................\part1
............................................\.....\part1_32
............................................\.....\........\model
............................................\.....\........\.....\mt48lc2m32b2.v
............................................\.....\........\rtl
............................................\.....\........\...\Command.v
............................................\.....\........\...\control_interface.v
............................................\.....\........\...\Params.v
............................................\.....\........\...\sdr_data_path.v
............................................\.....\........\...\sdr_sdram.v
............................................\.....\........\sim
............................................\.....\........\...\Command.v
............................................\.....\........\...\control_interface.v
............................................\.....\........\...\mt48lc2m32b2.v
............................................\.....\........\...\Params.v
............................................\.....\........\...\sd32try.cr.mti
............................................\.....\........\...\sd32try.mpf
............................................\.....\........\...\sdram_test_tb.v
............................................\.....\........\...\sdr_data_path.v
............................................\.....\........\...\sdr_sdram.v
............................................\.....\........\...\sdtry.cr.mti
............................................\.....\........\...\vsim.wlf
............................................\.....\........\...\wave.do
............................................\.....\........\...\work
............................................\.....\........\...\....\command
............................................\.....\........\...\....\.......\verilog.asm
............................................\.....\........\...\....\.......\_primary.dat
............................................\.....\........\...\....\.......\_primary.vhd
............................................\.....\........\...\....\control_interface
............................................\.....\........\...\....\.................\verilog.asm
............................................\.....\........\...\....\.................\_primary.dat
............................................\.....\........\...\....\.................\_primary.vhd
............................................\.....\........\...\....\mt48lc2m32b2
............................................\.....\........\...\....\............\verilog.asm
............................................\.....\........\...\....\............\_primary.dat
............................................\.....\........\...\....\............\_primary.vhd
............................................\.....\........\...\....\sdram_test_tb
............................................\.....\........\...\....\.............\verilog.asm
............................................\.....\........\...\....\.............\_primary.dat
............................................\.....\........\...\....\.............\_primary.vhd
............................................\.....\........\...\....\sdr_data_path
............................................\.....\........\...\....\.............\verilog.asm
............................................\.....\........\...\....\.............\_primary.dat
............................................\.....\........\...\....\.............\_primary.vhd
............................................\.....\........\...\....\sdr_sdram
............................................\.....\........\...\....\.........\verilog.asm
............................................\.....\........\...\....\.........\_primary.dat
............................................\.....\........\...\....\..

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