FPGA development board supporting Verilog code. Chips for the Mars EP1C6F. Some of the source interface. Including 7 digital tube, I2C communications.

接口实验
........\12864lcd
........\........\cmp_state.ini
........\........\db
........\........\..\altsyncram_g5j.tdf
........\........\..\altsyncram_h5j.tdf
........\........\..\lcd0.asm.qmsg
........\........\..\lcd0.cbx.xml
........\........\..\lcd0.cmp.cdb
........\........\..\lcd0.cmp.hdb
........\........\..\lcd0.cmp.qrpt
........\........\..\lcd0.cmp.rdb
........\........\..\lcd0.cmp.tdb
........\........\..\lcd0.cmp0.ddb
........\........\..\lcd0.dbp
........\........\..\lcd0.db_info
........\........\..\lcd0.eco.cdb
........\........\..\lcd0.fit.qmsg
........\........\..\lcd0.hier_info
........\........\..\lcd0.hif
........\........\..\lcd0.map.cdb
........\........\..\lcd0.map.hdb
........\........\..\lcd0.map.qmsg
........\........\..\lcd0.pre_map.cdb
........\........\..\lcd0.pre_map.hdb
........\........\..\lcd0.psp
........\........\..\lcd0.rtlv.hdb
........\........\..\lcd0.rtlv_sg.cdb
........\........\..\lcd0.rtlv_sg_swap.cdb
........\........\..\lcd0.sgdiff.cdb
........\........\..\lcd0.sgdiff.hdb
........\........\..\lcd0.signalprobe.cdb
........\........\..\lcd0.sld_design_entry.sci
........\........\..\lcd0.sld_design_entry_dsc.sci
........\........\..\lcd0.smp_dump.txt
........\........\..\lcd0.syn_hier_info
........\........\..\lcd0.tan.qmsg
........\........\..\lcd0_sim.qrpt
........\........\..\rom0.hdl.mif
........\........\..\rom1.hdl.mif
........\........\..\rom2.hdl.mif
........\........\..\rom3.hdl.mif
........\........\lcd0.asm.rpt
........\........\lcd0.done
........\........\lcd0.fit.eqn
........\........\lcd0.fit.rpt
........\........\lcd0.fit.summary
........\........\lcd0.flow.rpt
........\........\lcd0.map.eqn
........\........\lcd0.map.rpt
........\........\lcd0.map.summary
........\........\lcd0.pin
........\........\lcd0.pof
........\........\lcd0.qpf
........\........\lcd0.qsf
........\........\lcd0.qws
........\........\lcd0.sim.rpt
........\........\lcd0.sof
........\........\lcd0.tan.rpt
........\........\lcd0.tan.summary
........\........\lcd0.v
........\........\lcd0.vwf
........\........\lcd0_assignment_defaults.qdf
........\1602LCD
........\.......\cmp_state.ini
........\.......\db
........\.......\..\altsyncram_7i92.tdf
........\.......\..\altsyncram_9i92.tdf
........\.......\..\altsyncram_ph92.tdf
........\.......\..\cntr_9v7.tdf
........\.......\..\cntr_f29.tdf
........\.......\..\cntr_gv7.tdf
........\.......\..\cntr_hv7.tdf
........\.......\..\cntr_ln7.tdf
........\.......\..\cntr_no8.tdf
........\.......\..\cntr_vt9.tdf
........\.......\..\decode_9ie.tdf
........\.......\..\lcd_v.asm.qmsg
........\.......\..\lcd_v.cbx.xml
........\.......\..\lcd_v.cmp.cdb
........\.......\..\lcd_v.cmp.hdb
........\.......\..\lcd_v.cmp.qrpt
........\.......\..\lcd_v.cmp.rdb
........\.......\..\lcd_v.cmp.tdb
........\.......\..\lcd_v.cmp0.ddb
........\.......\..\lcd_v.dbp
........\.......\..\lcd_v.db_info
........\.......\..\lcd_v.eco.cdb
........\.......\..\lcd_v.fit.qmsg
........\.......\..\lcd_v.hier_info
........\.......\..\lcd_v.hif
........\.......\..\lcd_v.map.cdb
........\.......\..\lcd_v.map.hdb
........\.......\..\lcd_v.map.qmsg
........\.......\..\lcd_v.pre_map.cdb
........\.......\..\lcd_v.pre_map.hdb
........\.......\..\lcd_v.psp
........\.......\..\lcd_v.rtlv.hdb
........\.......\..\lcd_v.rtlv_sg.cdb
........\.......\..\lcd_v.rtlv_sg_swap.cdb

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