Introduction - If you have any usage issues, please Google them yourself
PWM control is a certain cycle, a different duty cycle square wave signal, when the duty cycle is high, higher motor speed, or lower motor speed. When the PWM waveform generated using FPGA, the FPGA internal resources only can be achieved, the figure one comparator output termination setting, the other linear incremental counter output termination. When the value of linear counter output is less than low-level settings, when the counter output is greater than high settings, so that by changing the settings can produce different duty cycle square wave signal, DC motor control to achieve the purpose of speed.
DC motor control circuit mainly by 2 parts, as shown in Figure 1:
FPGA in the PWM pulse width modulation signal generator circuit
Chiang Kai-shek FPGA/reverse direction control circuit