Up to 16-bit adder implementation, the working environment at ISE, modesim, the more detailed routines!

adder
.....\ise
.....\...\adder
.....\...\.....\.untf
.....\...\.....\adder.bgn
.....\...\.....\adder.bit
.....\...\.....\adder.bld
.....\...\.....\adder.cmd_log
.....\...\.....\adder.dhp
.....\...\.....\adder.drc
.....\...\.....\adder.lfp
.....\...\.....\adder.lso
.....\...\.....\adder.mrp
.....\...\.....\adder.nc1
.....\...\.....\adder.ncd
.....\...\.....\adder.ngc
.....\...\.....\adder.ngd
.....\...\.....\adder.ngm
.....\...\.....\adder.ngr
.....\...\.....\adder.npl
.....\...\.....\adder.pad
.....\...\.....\adder.pad_txt
.....\...\.....\adder.par
.....\...\.....\adder.pcf
.....\...\.....\adder.placed_ncd_tracker
.....\...\.....\adder.prj
.....\...\.....\adder.routed_ncd_tracker
.....\...\.....\adder.stx
.....\...\.....\adder.syr
.....\...\.....\adder.twr
.....\...\.....\adder.twx
.....\...\.....\adder.ucf
.....\...\.....\adder.ucf.untf
.....\...\.....\adder.ut
.....\...\.....\adder.v
.....\...\.....\adder.xpi
.....\...\.....\adder_map.ncd
.....\...\.....\adder_map.ngm
.....\...\.....\adder_pad.csv
.....\...\.....\adder_pad.txt
.....\...\.....\adder_vhdl.prj
.....\...\.....\automake.log
.....\...\.....\bitgen.ut
.....\...\.....\xst
.....\...\.....\...\work
.....\...\.....\...\....\hdllib.ref
.....\...\.....\...\....\vlg54
.....\...\.....\...\....\.....\adder.bin
.....\...\.....\_ngo
.....\...\.....\....\netlist.lst
.....\...\.....\__projnav
.....\...\.....\.........\adder.gfl
.....\...\.....\.........\adder.xst
.....\...\.....\.........\adder_flowplus.gfl
.....\...\.....\.........\adder_ncdTOut_tcl.rsp
.....\...\.....\.........\bitgen.rsp
.....\...\.....\.........\ednTOngd_tcl.rsp
.....\...\.....\.........\map.log
.....\...\.....\.........\nc1TOncd_tcl.rsp
.....\...\.....\.........\par.log
.....\...\.....\.........\parentAssignPackagePinsApp_tcl.rsp
.....\...\.....\.........\posttrc.log
.....\...\.....\.........\runXst_tcl.rsp
.....\...\.....\__projnav.log
.....\modelsim
.....\........\adder.cr.mti
.....\........\adder.mpf
.....\........\vsim.wlf
.....\........\work
.....\........\....\adder
.....\........\....\.....\verilog.asm
.....\........\....\.....\_primary.dat
.....\........\....\.....\_primary.vhd
.....\........\....\tb_adder
.....\........\....\........\verilog.asm
.....\........\....\........\_primary.dat
.....\........\....\........\_primary.vhd
.....\........\....\_info
.....\rtl
.....\...\adder.v
.....\...\tb_adder.v

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