Gate AND in VHDL (Quartus).

Bramka_and
..........\Block1.bdf
..........\bramka.done
..........\bramka.flow.rpt
..........\bramka.map.rpt
..........\bramka.map.summary
..........\bramka.qpf
..........\bramka.qsf
..........\bramka.qws
..........\bramka.sim.rpt
..........\bramka.vhd
..........\bramka.vhd.bak
..........\bramka.vwf
..........\db
..........\..\bramka.cbx.xml
..........\..\bramka.cmp.rdb
..........\..\bramka.dbp
..........\..\bramka.db_info
..........\..\bramka.eco.cdb
..........\..\bramka.fnsim.cdb
..........\..\bramka.fnsim.hdb
..........\..\bramka.fnsim.qmsg
..........\..\bramka.hier_info
..........\..\bramka.hif
..........\..\bramka.map.bpm
..........\..\bramka.map.cdb
..........\..\bramka.map.ecobp
..........\..\bramka.map.hdb
..........\..\bramka.map.logdb
..........\..\bramka.map.qmsg
..........\..\bramka.map_bb.cdb
..........\..\bramka.map_bb.hdb
..........\..\bramka.map_bb.logdb
..........\..\bramka.pre_map.cdb
..........\..\bramka.pre_map.hdb
..........\..\bramka.psp
..........\..\bramka.pss
..........\..\bramka.rtlv.hdb
..........\..\bramka.rtlv_sg.cdb
..........\..\bramka.rtlv_sg_swap.cdb
..........\..\bramka.sgdiff.cdb
..........\..\bramka.sgdiff.hdb
..........\..\bramka.sim.cvwf
..........\..\bramka.sim.hdb
..........\..\bramka.sim.qmsg
..........\..\bramka.sim.rdb
..........\..\bramka.simfam
..........\..\bramka.sld_design_entry.sci
..........\..\bramka.sld_design_entry_dsc.sci
..........\..\bramka.syn_hier_info
..........\..\bramka.tis_db_list.ddb
..........\..\prev_cmp_bramka.qmsg
..........\..\prev_cmp_bramka.sim.qmsg
..........\..\wed.wsf

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