FPGA read data from the FIFO and upload it to dual-port ram Medium.

connect20090223
...............\actgen
...............\connect20090223.prj
...............\constraint
...............\designer
...............\........\impl1
...............\........\.....\connect.tcl
...............\........\.....\designer_genhdl.log
...............\........\.....\impl.prj_des
...............\........\.....\simulation
...............\hdl
...............\...\connect.vhd
...............\...\dpram_w.vhd
...............\...\fifo_r.vhd
...............\package
...............\phy_synthesis
...............\simulation
...............\..........\meminit.dat
...............\..........\modelsim.ini
...............\..........\modelsim.log
...............\..........\postsynth
...............\..........\.........\connect
...............\..........\.........\.......\def_arch.dat
...............\..........\.........\.......\def_arch.psm
...............\..........\.........\.......\_primary.dat
...............\..........\.........\dpram_w
...............\..........\.........\.......\def_arch.dat
...............\..........\.........\.......\def_arch.psm
...............\..........\.........\.......\_primary.dat
...............\..........\.........\fifo_r
...............\..........\.........\......\def_arch.dat
...............\..........\.........\......\def_arch.psm
...............\..........\.........\......\_primary.dat
...............\..........\.........\testbench
...............\..........\.........\.........\one.dat
...............\..........\.........\.........\one.psm
...............\..........\.........\.........\_primary.dat
...............\..........\.........\_info
...............\..........\presynth
...............\..........\........\connect
...............\..........\........\.......\one.dat
...............\..........\........\.......\one.psm
...............\..........\........\.......\_primary.dat
...............\..........\........\dpram_w
...............\..........\........\.......\one.dat
...............\..........\........\.......\one.psm
...............\..........\........\.......\_primary.dat
...............\..........\........\fifo_r
...............\..........\........\......\one.dat
...............\..........\........\......\one.psm
...............\..........\........\......\_primary.dat
...............\..........\........\testbench
...............\..........\........\.........\one.dat
...............\..........\........\.........\one.psm
...............\..........\........\.........\_primary.dat
...............\..........\........\_info
...............\..........\run.do
...............\..........\vsim.wlf
...............\stimulus
...............\........\testbench.vhd
...............\........\testbench.vhd.bak
...............\synthesis
...............\.........\.recordref
...............\.........\connect.areasrr
...............\.........\connect.edn
...............\.........\connect.sdf
...............\.........\connect.srd
...............\.........\connect.srm
...............\.........\connect.srr
...............\.........\connect.srs
...............\.........\connect.tlg
...............\.........\connect.vhd
...............\.........\connect_sdc.sdc
...............\.........\connect_syn.prj
...............\.........\cur_state.txt
...............\.........\stdout.log
...............\.........\syntmp
...............\.........\......\connect.msg
...............\.........\......\connect.plg
...............\.........\traplog.tlg
...............\viewdraw
...............\........\sch
...............\........\sym
...............\........\vf
...............\........\..\project.lst
...............\........\viewdraw.ini
...............\........\wir
...............\时序图.bmp

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