VHDL prepared based on the SDR-SDRAM controller programming, is now commonly used in industry RAM controller

doc
...\readme.txt
...\sdr_sdram.pdf
model
.....\io_utils.vhd
.....\mt48lc8m16a2.vhd
.....\mt48lc8m16a2.zip
.....\mti_pkg.vhd
.....\stdlogar.vhd
.....\util1164.vhd
route
.....\pll1.vhd
.....\sdr_sdram.csf
.....\sdr_sdram.esf
.....\sdr_sdram.vqm
simulation
..........\APEX20KE_MF.VHD
..........\io_utils.vhd
..........\lpm_pack.vhd
..........\modelsim.ini
..........\mt48lc8m16a2.vhd
..........\mti_pkg.vhd
..........\readme.txt
..........\sdr_sdram_tb.vhd
..........\stdlogar.vhd
..........\util1164.vhd
..........\work
..........\....\altcam
..........\....\......\behave.dat
..........\....\......\behave.psm
..........\....\......\_primary.dat
..........\....\altclklock
..........\....\..........\behavior.dat
..........\....\..........\behavior.psm
..........\....\..........\_primary.dat
..........\....\altlvds_rx
..........\....\..........\behavior.dat
..........\....\..........\behavior.psm
..........\....\..........\_primary.dat
..........\....\altlvds_tx
..........\....\..........\behavior.dat
..........\....\..........\behavior.psm
..........\....\..........\_primary.dat
..........\....\command
..........\....\.......\rtl.dat
..........\....\.......\rtl.psm
..........\....\.......\_primary.dat
..........\....\control_interface
..........\....\.................\rtl.dat
..........\....\.................\rtl.psm
..........\....\.................\_primary.dat
..........\....\io_utils
..........\....\........\body.dat
..........\....\........\body.psm
..........\....\........\_primary.dat
..........\....\........\_vhdl.psm
..........\....\mt48lc8m16a2
..........\....\............\behave.dat
..........\....\............\behave.psm
..........\....\............\_primary.dat
..........\....\mti_pkg
..........\....\.......\body.dat
..........\....\.......\body.psm
..........\....\.......\_primary.dat
..........\....\.......\_vhdl.psm
..........\....\pll1
..........\....\....\syn.dat
..........\....\....\syn.psm
..........\....\....\_primary.dat
..........\....\sdr_data_path
..........\....\.............\rtl.dat
..........\....\.............\rtl.psm
..........\....\.............\_primary.dat
..........\....\sdr_sdram
..........\....\.........\rtl.dat
..........\....\.........\rtl.psm
..........\....\.........\_primary.dat
..........\....\sdr_sdram_tb
..........\....\............\rtl.dat
..........\....\............\rtl.psm
..........\....\............\_primary.dat
..........\....\std_logic_arith
..........\....\...............\body.dat
..........\....\...............\body.psm
..........\....\...............\_primary.dat
..........\....\...............\_vhdl.psm
..........\....\util_1164
..........\....\.........\body.dat
..........\....\.........\body.psm
..........\....\.........\_primary.dat
..........\....\.........\_vhdl.psm
..........\....\_info
source
......\Command.vhd
......\control_interface.vhd
......\pll1.vhd
......\sdr_data_path.vhd
......\sdr_sdram.vhd
synthesis
.........\synplicity

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