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【Other】 XC3S500EPQ208 DL : 0: Xilinx SPARTAN3E design guide line
Update : 2024-05-18 Size : 26624 Publisher : 凌峰
【Software Engineering】 VHDL DL : 0: 本系统使用VHDL语言进行设计，采用自上向下的设计方法。目标器件选用Xilinx公司的FPGA器件，并利用Xilinx ISE 7.1 进行VHDL程序的编译与综合，然后用Modelsim Xilinx Edition 6.1进行功能仿真和时序仿真。-The system design using VHDL language, using top-down design method. Selection of the target device Xilinx
Update : 2024-05-18 Size : 297984 Publisher : 西西
【Documents】 designconstraint DL : 0: FPGA高级设计方法-约束 (xilinx公司培训资料)-Senior FPGA Design Method- bound (xilinx corporate training information)
Update : 2024-05-18 Size : 374784 Publisher : mingqi
【ARM-PowerPC-ColdFire-MIPS】 CPLD DL : 0: 在文件夹YL2440_CPLD中有做好的CPLD工程,请用Xilinx ISE 6.2打开.-In the folder have to do a good job YL2440_CPLD the CPLD project, please open the Xilinx ISE 6.2.
Update : 2024-05-18 Size : 686080 Publisher : gaofeng
【Software Engineering】 KCPSM3_doc_1 DL : 0: 实验1：Xilinx软件平台设计流程实验 Spartan-3E目标板的初学者组件 by Picoblaze -Experiment 1: Xilinx software platform design flow experiment Spartan-3E target board Components of the beginner by Picoblaze
Update : 2024-05-18 Size : 1692672 Publisher : 王斯弘
【VHDL-FPGA-Verilog】 xilinxUSB DL : 0: XILINX USB程序-XILINX USB program
Update : 2024-05-18 Size : 154624 Publisher :
【Streaming Mpeg4】 dsp48macro_macfir DL : 0: xilinx embedded system: FIR design example.
Update : 2024-05-18 Size : 29696 Publisher : ylwang
【Software Engineering】 guiden-to-write-efficient-testbench DL : 0: 这是一个xilinx公司发布的写testbenth的入门向导，指导我们快速高效的写自己的testbenth，从而改进我们的仿真效果。 -This is a Xilinx Inc. released testbenth write entry wizard, guiding us to quickly and efficiently write their own testbenth, in order to improve our simulation effect.
Update : 2024-05-18 Size : 197632 Publisher : 罗肖
【Other】 vietro-pro DL : 0: 精心收集的xilinx公司的vietro pro系列FPGA的datasheet和usreguide，这两篇技术文档是我们使用该系列芯片FPGA的主要参考手册！-Carefully collected vietro pro Xilinx s FPGA-Series datasheet and usreguide, these two technical documentation is that we use the series FPGA chip main reference manual!
Update : 2024-05-18 Size : 4184064 Publisher : 罗肖
【VHDL-FPGA-Verilog】 Lcddisplay DL : 0: Xilinx sparten3E Lcd显示程序-Xilinx sparten3E Lcd display program
Update : 2024-05-18 Size : 1024 Publisher : ronghy
【VHDL-FPGA-Verilog】 PS2 DL : 0: Xilinx sparten3E 键盘和开发板的通信和LCD的字符显示-Xilinx sparten3E the keyboard and the development board of the Communications and character LCD display
Update : 2024-05-18 Size : 2048 Publisher : ronghy
【VHDL-FPGA-Verilog】 RS232 DL : 0: xilinx Sparten3E 串行通信及lcd字符显示-xilinx Sparten3E characters serial communication and lcd display
Update : 2024-05-18 Size : 2048 Publisher : ronghy
【VHDL-FPGA-Verilog】 ledwater DL : 0: 利用xilinx，完成流水灯发光二极管显示，-Use xilinx, the completion of light-emitting diode light water show
Update : 2024-05-18 Size : 41984 Publisher : haolj
【VHDL-FPGA-Verilog】 traffic DL : 0: xilinx完成一个模拟的十字路口交通信号灯，主干道上的绿灯时间为30s，支干道的绿灯时间为30s，且交通灯从绿变红时，有6s黄灯亮的时间间隔。当然每种状态的倒计时的时间值应显示到LED数码管上。-Xilinx completed in a simulated traffic lights at a crossroads, a main road on the green time for the 30s, branch roads green time for 30s, and red traffic lights from green when 6s yellow light time interval. Of course, each state s countdown time value should be shown on the LED digital tube.
Update : 2024-05-18 Size : 95232 Publisher : haolj
【VHDL-FPGA-Verilog】 fosc DL : 0: xilinx实现4位频率计，可测量从1HZ到9999HZ的频率信号，并将被测的信号频率输出显示到实验仪的数码管上。-Xilinx achieve Cymometer 4, measurable, from 1Hz to 9999HZ frequency signals, and measured the frequency of the output signal indicates that the experimental instrument digital tube.
Update : 2024-05-18 Size : 88064 Publisher : haolj
【VHDL-FPGA-Verilog】 pwm1 DL : 0: xilinx设计并完成一个10位的D/F转换器，输入的数字量分别由按键K1,K2来调节，其中K1完成加1功能，而K2则完成减1功能，并把转换的结构西哦女冠到BUZZ蜂鸣器上。-Xilinx design and complete a 10-bit D/F converter, the digital input from the keys K1, K2 to regulate, including the completion of plus 1 functions K1, K2 and completed by 1 functions, and to convert the structure of the West Oh F BUZZ crown to the buzzer on.
Update : 2024-05-18 Size : 79872 Publisher : haolj
【VHDL-FPGA-Verilog】 ml505_pcie_x1_plus DL : 0: Xilinx 公司PCI Express IP核应用参考设计。通过这个样例，用户可以掌握PCI Express应用设计的一般方法，了解PCI Express的工作原理。-Xilinx Inc. PCI Express IP core reference design applications. Through this example, the user can master the application of the design of PCI Express general approach to understand the working principle of PCI Express.
Update : 2024-05-18 Size : 1798144 Publisher : daniel J
【VHDL-FPGA-Verilog】 xst3_IDE DL : 0: Access IDE harddisk by Xilinx FPGA Support PIO2-err
Update : 2024-05-18 Size : 33792 Publisher : ronsullivan
【Other】 JTAG DL : 0: XILINX AND MSP430 PCB FOR JTAG AND ORIGINAL FILES
Update : 2024-05-18 Size : 62464 Publisher : FEF
【Other】 pcie_ml555x4_prj DL : 0: 已经在xilinx的ML555开发板上实现的PCIEx4的设计，其中带有DMA功能。满足pciexpress1.0规范。-Already in the Xilinx ML555 development board to achieve PCIEx4 design, which features with DMA. Pciexpress1.0 meet the specification.
Update : 2024-05-18 Size : 4633600 Publisher : nuaa

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