Search - vhdl

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【VHDL-FPGA-Verilog】 SRAM@DMA实验 DL : 0: ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器，然后NIOS　SHELL下C 语言运行。实验SRAM和DMA调度-Altera NIOS processor experiments QUARTUS using VHDL compiler into processor, then NIOS SHELL C language runtime. Experimental SRAM and DMA Scheduling
Update : 2024-05-17 Size : 33792 Publisher : xf
【VHDL-FPGA-Verilog】 SPI接口音频Codec实验 DL : 0: ALTERA NIOS处理器，VHDL语言在QUARTUS编译通过，然后有C语言在NIOS SHELL下驱动，实验音频解码-Altera NIOS processor, the QUARTUS VHDL compiler, then the C language under NIOS SHELL-driven, experimental audio decoder
Update : 2024-05-17 Size : 34816 Publisher : xf
【VHDL-FPGA-Verilog】 frequency发生器 DL : 0: vhdl语言实现的频率发生器，可以产生不同的频率-A frequency generator wirriten by VHDL, which can generate different frequecies.
Update : 2024-05-17 Size : 1024 Publisher : xf
【VHDL-FPGA-Verilog】 ASKDASK DL : 0: ask调制，基于VHDL仿真平台，解调同样给出，此程序经过验证-ask modulation, based on VHDL simulation platform, demodulator is the same, this procedure proven
Update : 2024-05-17 Size : 96256 Publisher : we
【ARM-PowerPC-ColdFire-MIPS】 leon2-1.0.30-xst.tar DL : 0: Leon2 CPU VHDL Source Code 欧洲航天局资助开发的LEON CPU,源码遵循GPL -Leon2 CPU VHDL Source Code European Space Agency funded the development of LEON CPU, followed source GPL
Update : 2024-05-17 Size : 1397760 Publisher : 笑雨
【VHDL-FPGA-Verilog】 CRC校验参考设计_xilinx_vhdl DL : 0: 可配置CRC参考设计 xilinx提供的VHDL-configurable CRC reference design for Xilinx VHDL
Update : 2024-05-17 Size : 49152 Publisher : 陈旭
【VHDL-FPGA-Verilog】 ZBT SRAM控制器参考设计vhdl_xilinx DL : 0: ZBT SRAM控制器参考设计，xilinx提供的VHDL源代码-ZBT SRAM controller reference design for Xilinx VHDL source code
Update : 2024-05-17 Size : 9216 Publisher : 陈旭
【VHDL-FPGA-Verilog】曼彻斯特编解码 Xilinx提供_vhdl DL : 0: 曼彻斯特编解码 Xilinx提供的VHDL的源代码-Manchester codec Xilinx provide VHDL source code
Update : 2024-05-17 Size : 10240 Publisher : 陈旭
【VHDL-FPGA-Verilog】 USB接口控制器参考设计_xilinx提供_vhdl DL : 0: USB接口控制器参考设计，xilinx提供的VHDL源代码-USB interface controller reference design for Xilinx VHDL source code
Update : 2024-05-17 Size : 460800 Publisher : 陈旭
【Embeded-SCM Develop】卷积码、CRC DL : 0: 卷积码的C源程序，包括编码器和译码器。还有一个是循环荣誉校验的vhdl]源码。-convolution of C source code, including the encoder and decoder. There is a cycle of the calibration honor VHDL] source.
Update : 2024-05-17 Size : 6144 Publisher : 潘华林
【VHDL-FPGA-Verilog】一些VHDL源代码 DL : 0: 内有波形发生器，加法器，经典双进程状态机，伪随机熟产生器，相应加法器的测试向量，16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM
Update : 2024-05-17 Size : 45056 Publisher : 蔡孟颖
【VHDL-FPGA-Verilog】 8位大小比较器 DL : 0: 8位大小比较器的VHDL源代码，Magnitude Comparator VHDL description of a 4-bit magnitude comparator with expansion inputs-eight compared with the size of the VHDL source code, Magnitude Comparator VHDL description of a 4-bit magnitude comparator inputs with expansion
Update : 2024-05-17 Size : 1024 Publisher : 蔡孟颖
【VHDL-FPGA-Verilog】一些译码器源代码 DL : 0: 内有LED译码器，汉明纠错译码器，地址译码器，最高优先译码器，双2－4译码器等VHDL的源代码-decoder, Hamming error correction decoder, address decoder, the highest priority decoder, dual 2-4 decoder such as VHDL source code
Update : 2024-05-17 Size : 4096 Publisher : 蔡孟颖
【Software Engineering】 ctsb DL : 0: 介绍了vhdl设计fpga时仿真和综合的过程，包括软件的应用和一些注意事项，相信会对大家有所帮助-introduced a VHDL design and simulation when they simply integrated process, including software applications and some attention to matters, we believe it will help
Update : 2024-05-17 Size : 415744 Publisher : 周玲玲
【Other】 ISE_chinese DL : 0: 通俗的介绍了ise的使用方法，对vhdl和verilog开发的初学者来说是不错的选择-popular introduction to the use of the method ideally, the VHDL and Verilog development of the newcomer is a good choice
Update : 2024-05-17 Size : 934912 Publisher : 周玲玲
【source in ebook】 SystemC片上系统设计源代码 DL : 0: SystemC片上系统设计的源代码：书籍介绍： SystemC是被实践证明的优秀的系统设计描述语言，它能够完成从系统到门级、从软件到硬件、从设计到验证的全部描述。SystemC 2.01已作为一个稳定的版本提交到IEEE，申请国际标准。本书为配合清华大学电子工程系SystemC相关课程的教学而编写。全书分9章，内容包括：硬件描述语言的发展史；SystemC出现的历史背景和片上系统设计方法学概述；SystemC的基本语法；SystemC的寄存器传输级设计和SystemC的可综合语言子集，以及根据作者设计经历归结的RTL设计准则和经验；接口、端口和通道等SystemC行为建模实例——片上总线系统；SystemC与VHDL/Verilog HDL的比较；SystemC的验证标准和验证方法学；SystemC开发工具SystemC_win、WaveViewer等，以及使用MATLAB进行SystemC算法模块的验证。每一章都精心编写了课后习题以配合教学的需要。本书可作为大学电子设计自动化（EDA）相关课程教材，也可供电子工程技术人员作为SystemC设计、应用开发的技术参考书。本书丰富的实例源代码特别适合初学者根据内容实际运行、体会，举一反三，以掌握SystemC进行应用系统设计。 -SystemC system on chip design source : books introduced : SystemC has been proven in practice is an excellent system design description language, it can be completed from the system level to the door, from hardware to software, from design to verification of all description. SystemC has 2.01 as a stable version submitted to the IEEE, the application of international standards. The book to tie in electronic engineering at Tsinghua University SystemC related courses and preparation of teaching. Book nine chapters, including : hardware description language development history; SystemC is the historical background and system-on-chip design methodology outlined; SystemC basic grammar; SystemC register-transfer-level design and synthesis of SystemC language subset, as well as design experience b
Update : 2024-05-17 Size : 2640896 Publisher : c.li
【VHDL-FPGA-Verilog】 sdr sdram controller DL : 0: ALTERA sdram vhdl与verilog参考设计-Altera SDRAM VHDL and Verilog reference design
Update : 2024-05-17 Size : 2458624 Publisher : 陈东平
【Browser Client】通信流程 DL : 0: vhdl的高级特性包括详细的特性分析能让初学者很好的了解VHDL-instantiate the advanced features include a detailed analysis of the characteristics allow beginners a good understanding of VHDL
Update : 2024-05-17 Size : 12288 Publisher : j
【SCM】 oc8051_design DL : 0: 这是用VHDL来设计80C51的开发过程和代码！处女作，大家一定要顶啊！-This is 80C51 VHDL design to the development process and code! The first time, we must Crack!
Update : 2024-05-17 Size : 323584 Publisher : 冯海
【VHDL-FPGA-Verilog】 CH1VHDL 数字电路参考书所有程序1 DL : 0: VHDL 与数字电路设计程序参考书所有程序 1-VHDL and digital circuit design process all the procedures a reference book
Update : 2024-05-17 Size : 13312 Publisher : 胡计划

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