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【SCM】 1335 DL : 0: /*=== === === === === === === === === === === === === SED1335驱动320x240图形液晶驱动演示程序接口情况表述： No: LCM ----- 52 --------------------- 1...VSS..... GND 地线 2...VDD..... +5V(VCC) 电源 3...VO ..... -Vadj Input 对比度负压调整输入 4...A0 ..... P2.0 寄存器选择信号,命令数据方式选择 5.../WR..... WR 写有效 6.../RD..... RD 读有效 7...D0 ..... P0.0 数据总线 D0 8...D1 ..... P0.1 数据总线 D1 9...D2 ..... P0.2 数据总线 D2 10..D3 ..... P0.3 数据总线 D3 11..D4 ..... P0.4 数据总线 D4 12..D5 ..... P0.5 数据总线 D5 13..D6 ..... P0.6 数据总线 D6 14..D7 ..... P0.7 数据总线 D7 15../CS .... GND 片选通信号，低电平有效.实际使用应编入地址 16../RES.... /RESET 复位信号，低电平有效，阻容式复位电路 17..VEE..... -Vout 逆变-22.5V 负电压输出 18..VSS..... GND 地线 0V-/*================================================ ============================== SED1335 320x240 graphic LCD driver driver demo Interface condition expression: No: LCM----- 52 --------------------- 1 ... VSS ..... GND Ground 2 ... VDD .....+5 V (VCC) power 3 ... VO .....-Vadj Input negative pressure to adjust the input contrast 4 ... A0 ..... P2.0 register select signal, the command mode selection data 5.../WR ..... WR to write effective 6.../RD ..... RD Reading effectively 7 ... D0 ..... P0.0 data bus D0 8 ... D1 ..... P0.1 data bus D1 9 ... D2 ..... P0.2 data bus D2 10 .. D3 ..... P0.3 data bus D3 11 .. D4 ..... P0.4 data bus D4 12 .. D5 ..... P0.5 data bus D5 13 .. D6 ..... P0.6 data bus D6 14 .. D7 ..... P0.7 data bus D7 15../CS .... GND chip strobe, active low. The actual use should be incorporated into the address 16../RES ..../RESET reset signal, active low, RC-reset circuit 17 .. VEE .....-Vout output negative voltage inverter-22.5V
Update : 2024-05-19 Size : 43008 Publisher : 无所畏
【matlab】 quiverc DL : 0: 在这个更新的代码，新功能，包括colorbar，samesize包括向量plottting... ％更新版本$日期：5月18日，2011年由梁枯盎斯蒂文斯技术学院％更新1：更改int8到Int16的colormap的是，当电流超过64个大，这将导致错误％更新2：加入 samesize 为使所有的向量samesize ％更新3：添加colorbar相应的开方的幅度（ü^2+ V键^ 2）％更新4：错误修复，当你为h = quiverc，这是行不通的。 ------------------------------------------------- ----------- -In this updated code,new features including colorbar, samesize vectors plottting are included Updated version $Date: May 18th,2011 by Liang Kuang at Stevens Institute of Tech Update 1: Change int8 to int16 when current colormap is bigger than 64,which will cause error Update 2: Added samesize for making all the vectors the samesize Update 3: Add colorbar corresponding the the magnitude of sqrt(u^2+v^2) Update 4: bug fixed,when you do h=quiverc, it doesn t work. ------------------------------------------------------------
Update : 2024-05-19 Size : 4096 Publisher : zzskzcau
【Data structs】 01bag_problem DL : 0: 特殊的01背包（原算法分析题4-3）问题描述：01背包是在N件物品取出若干件放在空间为C的背包里，每件物品的体积为W1，W2……Wn，与之相对应的价值为P1,P2……Pn，并取得最大价值。普通的01背包中物品的重量和价值没有明确的关系，这里定义一种特殊的01背包：向背包中放入的物品的价值和体积成反比，也就是价值越高，体积越小，注意这里物品价值和体积的乘积并不是固定值。例如：如下的物品满足这个“特殊的01背包”,5件物品: 物品1,价值 v=6,体积w=20 物品2,价值 v=1,体积w=60 物品3,价值 v=20,体积w=3 物品4,价值 v=15,体积w=15 物品5,价值 v=99,体积w=1 假如我有一个容量为c的背包,c=20，那么选择物品3、4、5可以获得最大价值134。 -01 bag problem
Update : 2024-05-19 Size : 671744 Publisher : 毛骏
【Software Engineering】 aaaa DL : 0: 一温度测量系统的测量值如下：（15分）输入温度值（摄氏）: 0.0, 0.5, 1.0, 1.5, 2.0, 2.5，3 输出电压值（V）: -4.90, 20.316, 40.726, 61.435, 82.181, 103.123，123.255 设计VI, 实现输入温度和输出电压之间的最佳线性拟合直线。-A temperature measurement system, measurements are as follows: (15 points) input temperature (Celsius): 0.0, 0.5, 1.0, 1.5, 2.0, 2.5,3 output voltage (V):-4.90, 20.316, 40.726, 61.435, 82.181 , 103.123,123.255 Design VI, the input temperature and output voltage between the best linear fit straight line.
Update : 2024-05-19 Size : 9216 Publisher : jermmy
【Mathimatics-Numerical algorithms】 Statistical-letters-number DL : 0: Description: 给定一段文章，请输出每个字母出现的次数。 Input: 只有一组输入数据，该数据大小<10KB。在文章中除最后一个字符外，只有小写字母、空格和换行符，没有另外的标点、数字和大写字母等。该文章以’#’结尾。 Output: 输出格式为“C A”，C为’a’..’z’中的字母，A为出现次数，C和A之间空一格。 Sample Input: here is the input this is the article# Sample Output: a 1 b 0 c 1 d 0 e 5 f 0 g 0 h 4 i 5 j 0 k 0 l 1 m 0 n 1 o 0 p 1 q 0 r 2 s 3 t 5 u 1 v 0 w 0 x 0 y 0 z 0 -Description: for a given section of the article, please output the number of occurrences of each letter. Input: only one set of input data, the data size & lt10KB. In the article, except the last character, only lowercase letters, spaces and line breaks, no other punctuation, numbers and uppercase letters. The article in ' #' at the end. Output: Output format is " CA" , C as ' a' .. ' z' in the letters, A is the number of occurrences, C and A space between. Sample Input: here is the input this is the article# Sample Output: a 1 b 0 c 1 d 0 e 5 f 0 g 0 h 4 i 5 j 0 k 0 l 1 m 0 n 1 o 0 p 1 q 0 r 2 s 3 t 5 u 1 v 0 w 0 x 0 y 0 z 0
Update : 2024-05-19 Size : 9216 Publisher : 沙魄郎君
【Software Engineering】 ADM2483 DL : 0: RS-485 transceiver with electrical data isolation Complies with ANSI TIA/EIA RS-485-A and ISO 8482: 1987(E) 500 kbps data rate Slew rate-limited driver outputs Low power operation: 2.5 mA max Suitable for 5 V or 3 V operations (VDD1) High common-mode transient immunity: >25 kV/μs True fail-safe receiver inputs Chatter-free power-up/power-down protection 256 nodes on bus Thermal shutdown protection Safety and regulatory approvals UL recognition: 2500 Vrms for 1 minute per UL 1577 CSA Component Acceptance Notice #5A VDE Certificate of Conformity DIN EN 60747-5-2 (VDE 0884 Rev. 2): 2003-01 DIN EN 60950 (VDE 0805): 2001-12 EN 60950: 2000 VIORM = 560 V peak Operating temperature range: − 40°C to +85°C -RS-485 transceiver with electrical data isolation Complies with ANSI TIA/EIA RS-485-A and ISO 8482: 1987 (E) 500 kbps data rate Slew rate-limited driver outputs Low power operation: 2.5 mA max Suitable for 5 V or 3 V operations (VDD1) High common-mode transient immunity:> 25 kV/μs True fail-safe receiver inputs Chatter-free power-up/power-down protection 256 nodes on bus Thermal shutdown protection Safety and regulatory approvals UL recognition: 2500 Vrms for 1 minute per UL 1577 CSA Component Acceptance Notice# 5A VDE Certificate of Conformity DIN EN 60747-5-2 (VDE 0884 Rev. 2): 2003-01 DIN EN 60950 (VDE 0805): 2001-12 EN 60950: 2000 VIORM = 560 V peak Operating temperature range:-40 ° C to+85 ° C
Update : 2024-05-19 Size : 200704 Publisher : houly
【Data structs】 DBMM DL : 0: 单表密码定义： 1、明表： A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 2、明文 they will arrive tomorrow 3、密钥 K=Monday 4、密码实现 1）将明文与密钥转为数字串： K=(12,14,13,3,0,24) M=(19,7,4,24,22,8,11,11,0,17,17,8,21,4,19,14,12,14,17,17,14,22,) 2）将明文数字串依密钥长度分段，并逐一与密钥数字相加（模26），得到密文数字串。 19 7 4 24 22 8… 12 14 13 3 0 24… 5 21 17 1 22 6 C=(5，21，17，1，22，6，23，25，13，20 。。。) 3）密文数字串转换为字母串 c=（FVRBWG XZNURG HSGRMM DFBZ） 5、解密：模26减运算 1） C=(5，21，17，1，22，6，23，25，13，20 。。。) 2）模26减运算 5 21 17 1 22 6 — 12 14 13 3 0 24… -7 7 4 -2 22 -18 + 26 26 26 26 26 26 M=（19 7 4 24 22 8…） 3）将M转换为字符串，得到明文。 they will arrive tomorrow-Single table code
Update : 2024-05-19 Size : 4096 Publisher : lss
【ELanguage】 CompilersPrinciplesTechniquesaTools DL : 0: 真正的经典了。能彻底理解的人才有可能更进一步。中文名: 编译原理英文名: Compilers: Principles, Techniques, and Tools (第2版) 作者:(美)Alfred V.Aho Monica S.Lam Ravi Sethi Jeffrey D.Ullman djvu 文件阅读器： Windjview: http://windjview.sourceforge.net/ 本书全面、深入地探讨了编译器设计方面的重要主题，包括词法分析、语法分析、语法制导定义和语法制导翻译、运行时刻环境、目标代码生成、代码优化技术、并行性检测以及过程间分析技术，并在相关章节中给出大量的实例。与上一版相比，本书进行了全面修订，涵盖了编译器开发方面最新进展。每章中都提供了大量的实例及参考文献。　　本书是编译原理课程方面的经典教材，内容丰富，适合作为高等院校计算机及相关专业本科生及研究生的编译原理课程的教材，也是广大技术人员的极佳参考读物。-contents: 1 Introduction 1.1 Language Processors 1.1.1 Exercises for Section 1.1 1.2 The Structure of a Compiler 1.2.1 Lexical Analysis 1.2.2 Syntax Analysis 1.2.3 Semantic Analysis 1.2.4 Intermediate Code Generation 1.2.5 Code Optimization 1.2.6 Code Generation 1.2.7 Symbol-Table Management 1.2.8 The Grouping of Phases into Passes 1.2.9 Compiler-Construction Tools 1.3 The Evolution of Programming Languages 1.3.1 The Move to Higher-level Languages 1.3.2 Impacts on Compilers 1.3.3 Exercises for Section 1.3 1.4 The Science of Building a Compiler 1.4.1 Modeling in Compiler Design and Implementation 1.4.2 The Science of Code Optimization 1.5 Applications of Compiler Technology 1.5.1 Implementation of High-Level Programming Languages 1.5.2 Optimizations for Computer Architectures 1.5.3 Design of New Computer Architectures 1.5.4 Program Translations 1.5.5 Software Productivity Tools 1.6 Programining Language Basics 1.6.1 Tile Static/Dynamic Distinction 1.6.2 E
Update : 2024-05-19 Size : 5895168 Publisher : 白起
【VHDL-FPGA-Verilog】 texisystem DL : 0: 以单片机为中央控制器，设计一台出租车计价系统。系统中的直流电源由车载电源提供，电源电压为+9V~+24V。行驶里程传感器不需要设计，假设它具有汽车每行使1km提供1000个脉冲信号的特性。显示器可以采用LED数码管或LCD液晶显示模块。应达到的技术指标： 1、白天、晚上分别设置不同的里程单价，两位数码显示“X.X”,并用一键控制转换及显示； 2、两位数码显示车辆行使的里程数“XX”； 3、营运起步价为5.00元，当小于3公里按起步价结算，当大于3公里时，按里程单价×里程数结算，并用三位数码显示“XX.X”； 4、一键控制总价清除及开始计价，即按一下系统开始计价，再按一下时总价被清除（即用按键模拟出租车上的“空车”指示牌功能）。 -Single-chip microcomputer as the central controller, the design of a taxi meter system. System in the DC source is vehicle power supply, power supply voltage of+9 V ~+24 V. No mileage sensor design, assuming it has a car 1km each exercise provides 1000 pulses features. LED digital tube display can be used or LCD display module. Should meet the technical specifications: 1, daytime, evening set different mileage unit, two digital display "XX", and conversion and with a key control Display 2, the exercise of two digital display vehicle mileage "XX" 3, the operation starting at 5.00 yuan, while less than 3 km at prices starting at settlement, when more than 3 km, priced according to mileage × mileage settlement, and with three digital display "XX.X" 4, a key control and began to clear the total valuation, that valuation system began clicking, and then click when the total is cleared (ie, simulated with a taxi on the button "empty" sign function).
Update : 2024-05-19 Size : 54272 Publisher : yangzhen
【VHDL-FPGA-Verilog】 texi DL : 0: 以单片机为中央控制器，设计一台出租车计价系统。系统中的直流电源由车载电源提供，电源电压为+9V~+24V。行驶里程传感器不需要设计，假设它具有汽车每行使1km提供1000个脉冲信号的特性。显示器可以采用LED数码管或LCD液晶显示模块。应达到的技术指标： 1、白天、晚上分别设置不同的里程单价，两位数码显示“X.X”,并用一键控制转换及显示； 2、两位数码显示车辆行使的里程数“XX”； 3、营运起步价为5.00元，当小于3公里按起步价结算，当大于3公里时，按里程单价×里程数结算，并用三位数码显示“XX.X”； 4、一键控制总价清除及开始计价，即按一下系统开始计价，再按一下时总价被清除（即用按键模拟出租车上的“空车”指示牌功能）。 -Single-chip microcomputer as the central controller, the design of a taxi meter system. System in the DC source is vehicle power supply, power supply voltage of+9 V ~+24 V. No mileage sensor design, assuming it has a car 1km each exercise provides 1000 pulses features. LED digital tube display can be used or LCD display module. Should meet the technical specifications: 1, daytime, evening set different mileage unit, two digital display "XX", and conversion and with a key control Display 2, the exercise of two digital display vehicle mileage "XX" 3, the operation starting at 5.00 yuan, while less than 3 km at prices starting at settlement, when more than 3 km, priced according to mileage × mileage settlement, and with three digital display "XX.X" 4, a key control and began to clear the total valuation, that valuation system began clicking, and then click when the total is cleared (ie, simulated with a taxi on the button "empty" sign function).
Update : 2024-05-19 Size : 74752 Publisher : yangzhen
【VHDL-FPGA-Verilog】 texismoke DL : 0: 以单片机为中央控制器，设计一台出租车计价系统。系统中的直流电源由车载电源提供，电源电压为+9V~+24V。行驶里程传感器不需要设计，假设它具有汽车每行使1km提供1000个脉冲信号的特性。显示器可以采用LED数码管或LCD液晶显示模块。应达到的技术指标： 1、白天、晚上分别设置不同的里程单价，两位数码显示“X.X”,并用一键控制转换及显示； 2、两位数码显示车辆行使的里程数“XX”； 3、营运起步价为5.00元，当小于3公里按起步价结算，当大于3公里时，按里程单价×里程数结算，并用三位数码显示“XX.X”； 4、一键控制总价清除及开始计价，即按一下系统开始计价，再按一下时总价被清除（即用按键模拟出租车上的“空车”指示牌功能）。 -Single-chip microcomputer as the central controller, the design of a taxi meter system. System in the DC source is vehicle power supply, power supply voltage of+9 V ~+24 V. No mileage sensor design, assuming it has a car 1km each exercise provides 1000 pulses features. LED digital tube display can be used or LCD display module. Should meet the technical specifications: 1, daytime, evening set different mileage unit, two digital display "XX", and conversion and with a key control Display 2, the exercise of two digital display vehicle mileage "XX" 3, the operation starting at 5.00 yuan, while less than 3 km at prices starting at settlement, when more than 3 km, priced according to mileage × mileage settlement, and with three digital display "XX.X" 4, a key control and began to clear the total valuation, that valuation system began clicking, and then click when the total is cleared (ie, simulated with a taxi on the button "empty" sign function).
Update : 2024-05-19 Size : 52224 Publisher : yangzhen
【SCM】 TLC5615[1] DL : 0: TLC5615C, TLC5615I 10-BIT DIGITAL-TO-ANALOG CONVERTERS -10-Bit CMOS Voltage Output DAC in an 8-Terminal Package 5-V Single Supply Operation 3-Wire Serial Interface High-Impedance Reference Inputs Voltage Output Range . . . 2 Times the Reference Input Voltage Internal Power-On Reset Low Power Consumption . . . 1.75 mW Max Update Rate of 1.21 MHz Settling Time to 0.5 LSB . . . 12.5 µ s Typ Monotonic Over Temperature Pin Compatible with the Maxim MAX515 ications Battery-Powered Test Instruments Digital Offset and Gain Adjustment Battery Operated/Remote Industrial Controls Machine and Motion Control Devices Cellular Telephones
Update : 2024-05-19 Size : 305152 Publisher : li
【SCM】 PowerView4_3_86_N2 DL : 0: IT设备电源质量测试仪直流测试功能需求目的及用途： 1、测试现有的交流电服务器是否能使用直流供电； 2、直流供电的电压范围； 3、直流供电后的功率；技术指标及安全要求： 1、测试仪直流输出电压范围：标称值240V，可调范围200～300 V。输出电压可设置。 2、输出电流10A。 3、稳压精度应优于±1 。直流输出端在0MHz～20MHz频带内的峰—峰值电压应不大于输出电压标称值的0.5 。 4、输出正负极与地需隔离。 5、在默认情况下，直流输出“正”极，对应于设备输入电源线的“N”端，直流输出“负”极对应于设备输入电源线的“L”端，设备输入电源线的“地”端与系统保护地可靠连接，如图A.1所示。应设计有某种装置（拨动开关或者自动），当需要正负极互换位置时，可以进行调整。 -IT equipment power quality tester dc testing functional requirements Purpose and use: 1, test the existing alternating current server whether can use the dc power supply 2, dc power supply voltage range 3, dc power supply of power after Technical indicators and safety requirements: 1, dc output voltage tester range: nominal value 240 V, adjustable range 200 ~ 300 V. Output voltage can be set up. 2, the output current 10 A. 3, voltage stabilizing precision should better than plus or minus 1 . Dc output terminal at 0 MHz ~ 20 MHz frequency band of the peak-peak voltage should be no more than 0.5 of the nominal value of output voltage. 4, output of anode and to need isolation. 5, by default, dc output "are" extremely, corresponding to the input power equipment of the "N" side, the dc output "negative" extremely corresponding to the input power equipment of the "L" side, the equipment input power "to" end and reliable connection system protected, as shown in figure a.1 as s
Update : 2024-05-19 Size : 12968960 Publisher : 张军
【VHDL-FPGA-Verilog】 System_Demons DL : 0: 0.最简单的SystemC程序：hello, world. 1.用SystemC实现D触发器的例子，同时也演示了如何生成VCD波形文件。 2.用SystemC实现同步FIFO的例子。这个FIFO是从同文件夹的fifo.v（verilog代码）翻译过来的。 3.如何在SystemC中实现延时（类似verilog中的#time）的例子。 4.SystemC文档《User Guide》中的例子。注意和文挡中稍有不同的是修改了packet.h文件，重载了=和<<操作符。这其实也演示了在sc_signal中如何使用用户自定义的struct。 5.构造函数带参数的例子。 6.轮转仲裁的例子。 7.使用类摸板的例子。 8.如何在模块中包含子模块。 9.SystemC的Transaction级验证示例。 10.如何trace一个数组 11.SystemC中使用测试向量文件输入的例子。 12.SystemC采用UDP/TCP通信的例子。 13.Cadence的ncsc的例子。 -0 most simple SystemC program: hello, world. A D flip-flop using SystemC example also demonstrates how to generate VCD waveform files. Synchronous FIFO example using SystemC. FIFO is from the same folder fifo.v (Verilog code) translated. Delay (similar to verilog# time). In SystemC examples. 4.SystemC document the "User Guide" in the example. Note the slightly different cultural block is modified the packet.h file, reload = << operator. In fact, this also demonstrates how to use user-defined struct in sc_signal. Constructor with parameters example. (6) examples of web arbitration. 7. The class Moban examples. 8 module contains a sub-module. 9.SystemC of Transaction-Level Verification example. 10 How to trace an array 11.SystemC use the example of the test vector file input. 12.SystemC using the example of the UDP/TCP communication. Examples of 13.Cadence the ncsc.
Update : 2024-05-19 Size : 532480 Publisher : sdd
【JSP/Java】 JSPv3.0 DL : 0: 欢迎使用JSPGenCMS(JSPGen内容管理系统)视频播客版，开始使用之前请仔细阅读以下说明： 1、若不是使用WATMServer服务环境，则需要下载组件包(最新的为：Jar20101022.zip )。下载地址：http://cms.jspgen.com 2、数据库安装成功后的默认链接用户名及密码都是root，网站后台管理默认登录用户名及密码都是jspgen，该用户具有最高权限，请及时修改该用户的密码。 3、发现浏览器弹出窗口被阻止，请更改浏览器设置，以便正常使用内容发布全屏功能！ 4、Flv文件夹内所有文件需上传至服务器，上传后请根据实际情况修改配置文件基本配置区的"主机地址"及"安装路径"部分。否则静态生成等功能容易出错。 5、系统数据表文件Flv.sql，必须导入。 6、官方地址：http://cms.jspgen.com 演示地址：http://v.21hong.com QQ服务客服：190582560，275886308 QQ帮组交流群：12349848、14996531 7、视频教程：http://v.21hong.com/html/content/1290337930000X100.html --------------------------------------------------------------- 注意：在升级前请做好数据库及网站文件备份!-JSP video podcasts
Update : 2024-05-19 Size : 8516608 Publisher : 张宁
【VHDL-FPGA-Verilog】 _1_turn_on_led DL : 0: verilog实例点亮LED[1]、LED[3]、LED[5]、LED[7] （1）源文件 turn_on_led.v （2）管脚分配 pins list.txt -verilog实例点亮LED[1]、LED[3]、LED[5]、LED[7] （1）源文件 turn_on_led.v （2）管脚分配 pins list.txt
Update : 2024-05-19 Size : 40960 Publisher : 李程序
【JSP/Java】 fushu DL : 0: 3. 定义一个复数(z=x+iy)类Complex，包含：两个属性：实部x和虚部y 默认构造函数 Complex()，设置x=0,y=0 构造函数：Complex(int i,int j) 显示复数的方法：showComp()将其显示为如： 5+8i或5-8i 的形式。求两个复数的和的方法：（参数是两个复数类对象，返回值是复数类对象）public Complex addComp(Complex C1,Complex C2) 求两个复数的差的方法：（参数是两个复数类对象，返回值是复数类对象）public Complex subComp(Complex C1,Complex C2) -. A class definition Point, represents a Point, public property have x and y, a method that Point coordinates show (), there are two arguments constructor respectively to x, y assignment, in the main method constructed of two objects, to create a method (getMiddle) to take two make the Point of the line of coordinate, parameters for 2 Point object, call this method after get a new Point, write Application, display the object coordinates. 1. Define a plural (z = x+ iy) kind of Complex, including: Two attributes: real part x and imaginary part y The default constructor Complex (), set x = 0, y = 0 The constructor: Complex (int I, int j) Show the plural method: showComp () will be the display for such as: 5+ 8 I or 5-8 I form. For two of the plural and methods: (parameters are two plural class object, the return value is a plural class object) public Complex addComp (Complex C1, Complex C2) For two of the plural of poor methods: (parameters are two plural class object, the return v
Update : 2024-05-19 Size : 3072 Publisher : 袁木
【SCM】 adda DL : 0: 文件名称: A/D实验--采样、存储和显示实验.ASM 文件标识: none 适用器件: 89C51 ①ADC0809的片选CS1连A15，RAM6116的片选CS3连A14。 ②要求在ADC0809的输入端加上不同的模拟信号，通过键盘输入ADC0809的通道号并启动A/D转换，采集N个（如N=256）数据存入外部RAM中，打开XDATA窗口，检查实验结果。注意：①在进行A/D采样前，应先检查ADC0809的参考电压是否正确。（要求ADC0809的参考电压值Vref = +5V，用万用表观察ADC0809芯片的12脚电压值。若不对，可调节实验板上的电位器W1来改变A/D的参考电压值）。 ②实验板上电位器W2可调节校准信号的值（注：实验板上校准信号已经连到通道7的IN7上）。 ③将AD采样的值送到RAM6116的0b000H开始单元中，同时在数码管上显示出来。 -File Name: A/D experiment- sampling, storage and display of experimental ASM File identification: none Applicable to devices: 89C51 ① the ADC0809 s chip select CS1 with A15-, A14, RAM6116 chip select CS3 even. The ② requirements with different analog signal input of the ADC0809, and start the channel number of the keyboard to enter the ADC0809 A/D converter, Acquisition of N (eg, N = 256) data are stored in external RAM, open the the XDATA window, check the experimental results. Note: ① The carrying out A/D sampling, you should first check ADC0809 reference voltage is correct. (For the ADC0809 reference voltage value Vref =+5 V, to observe the ADC0809 chip 12-pin voltage with a multimeter. If you are right, the experimental board adjustable potentiometer W1 to change the A/D reference voltage value). ② The board potentiometer W2 to adjust the value of the calibration signal (Note: The experimental on-board calibration signal is connected to channel 7 IN7). (3) the value of th
Update : 2024-05-19 Size : 1024 Publisher : ilkb
【Algorithm】 turn-albo-to-ruma-data DL : 0: 输入一个不确定位数的数字，将其转化罗马数字，用"X","I","II","III","IV","V","VI","VII","VIII","IX"代表0,1，2,3,4,5,6,7,8,9的罗马数字。程序不是太严谨，和实际的表示（10应该用X表示，五十用C表示等等）也有差距。受定义类型的限制，位数不能无限多。程序共用了三种方法，注释掉的是两种麻烦并且占内存多（其实可以修改成和第一种方法占内存一样多）的方法-Enter an uncertain number of digits, Roman numerals, with the " X" , " " II " ," III " ," IV " ," V " ," VI, VII, " VIII of " ," IX " on behalf of 0,1,2,3,4,5,6,7,8,9 of Roman numerals. The program is not too rigorous, and practical (10 X represents fifty C represents, etc.) is also a gap. Limit of the defined type, the median can not be unlimited. Program three methods, comment out the two cumbersome and accounted for memory (in fact, could be modified to the first method accounts for as much) memory
Update : 2024-05-19 Size : 9216 Publisher : tanruibao
【Books】 AMS1117 DL : 0: AMS1117是一个正向低压降稳压器，在1A电流下压降为1.2V。 AMS1117有两个版本:固定输出版本和可调版本,固定输出电压为1.5V、1.8V、2.5V、2.85V、3.0V、3.3V、 5.0V,具有1％的精度；固定输出电压为1.2V的精度为2 。-AMS1117 is a positive low dropout regulator, the pressure drop in the 1A current 1.2V. The AMS1117 There are two versions: fixed output version and an adjustable version and fixed output with a voltage of 1.5V, 1.8V, 2.5V, 2.85V, 3.0V, 3.3V, 5.0V fixed output voltage, with 1 accuracy 1.2 V and an accuracy of 2 .
Update : 2024-05-19 Size : 606208 Publisher : 罗梦颖

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