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【VHDL-FPGA-Verilog】 adc8888 DL : 0: 8位的a/d行为模型，可以应用于modelsim等环境下的仿真，不可综合。-eight of the a/d behavior model can be applied to other environments modelsim the simulation, not comprehensive.
Update : 2024-05-20 Size : 2048 Publisher : 江浩
【VHDL-FPGA-Verilog】 sram__ DL : 0: 静态随机读取存储器行为模型，可以应用于modelsim环境的仿真。-static random acts of reading memory model can be applied to the simulation environment modelsim.
Update : 2024-05-20 Size : 2048 Publisher : 江浩
【VHDL-FPGA-Verilog】 oem_man DL : 0: Modelsim使用教程，英文版，从新建工程到完成仿真讲的非常详细，适合初学者。-Modelsim use guides, in English, from new construction to be completed simulation in a very detailed, for beginners.
Update : 2024-05-20 Size : 2044928 Publisher : snake
【VHDL-FPGA-Verilog】 modelsim_guide_cn DL : 0: modelsim操作指导很适合入门有实例-modelsim operation guidance is very suitable example of a portal
Update : 2024-05-20 Size : 342016 Publisher : 大师
【VHDL-FPGA-Verilog】 fulleradder DL : 0: 本程序以Modelsim为开发平台，采用VHDL为开发语言，实现了简单的全加器．适合初学Modelsim的同行-Modelsim the procedures for the development of a platform for the development of VHDL language, achieving a simple full adder. Suitable for a novice counterparts Modelsim
Update : 2024-05-20 Size : 30720 Publisher : 刘小军
【VHDL-FPGA-Verilog】 modelsim_userguide DL : 0: 仿真软件MODELSIM的用户使用手册，对MODELSIM用户有很大帮助。-MODELSIM simulation software users manuals, MODELSIM users to be of much help.
Update : 2024-05-20 Size : 3899392 Publisher : liujie
【VHDL-FPGA-Verilog】 Freq_counter DL : 0: 本代码介绍了使用VHDL开发FPGA的一般流程，最终采用了一种基于FPGA的数字频率的实现方法。该设计采用硬件描述语言VHDL，在软件开发平台ISE上完成，可以在较高速时钟频率（100MHz）下正常工作。该设计的频率计能准确的测量频率在1Hz到100MHz之间的信号。使用ModelSim仿真软件对VHDL程序做了仿真，并完成了综合布局布线，最终下载到芯片Spartan-II上取得良好测试效果。-the code on the FPGA using VHDL development of the general process, finally adopted a FPGA-based digital frequency method. The design using VHDL hardware description language, the software development platform ISE completed, the higher speed clock frequency (100MHz) under normal work. The design of the frequency meter can be accurately measured in a frequency of 100MHz between Hz signal. Use ModelSim VHDL simulation software to do the simulation process, and completed a comprehensive layout cabling, downloaded to the final chip Spartan-II made good on the test results.
Update : 2024-05-20 Size : 515072 Publisher : 许的开
【Software Engineering】 Modelsim_houfangzhen DL : 0: this is a book of modelsim hou fang zhen,it is very good for study modelsim,-this is a book of modelsim hou fang zhen, it is very good for study modelsim.
Update : 2024-05-20 Size : 429056 Publisher : 王明
【VHDL-FPGA-Verilog】 RISCMCU DL : 0: riscMCU的VHDL实现，内附有modelsim仿真testbench和文档说明-riscMCU VHDL, modelsim containing a simulation testbench and documentation shows
Update : 2024-05-20 Size : 594944 Publisher : wutailiang
【VHDL-FPGA-Verilog】 CPUNEW DL : 0: MODELSIM开发的模拟CPU，用VHDL语言描述，采用累加结构-ModelSim simulation developed CPU, using VHDL language description of the structure of the use of cumulative
Update : 2024-05-20 Size : 50176 Publisher : yyy
【VHDL-FPGA-Verilog】 vhdlYONGHUSHOUCE DL : 0: 非常优秀的国外VHDL设计教程，可进行MODELSIM模拟等操作-Excellent foreign VHDL design tutorial, it can conduct operations such as ModelSim Simulation
Update : 2024-05-20 Size : 2766848 Publisher : yyy
【VHDL-FPGA-Verilog】 Fir DL : 0: 11 阶FIR 数字滤波器,verolog描述，通过modelsim 6.0 仿真，Quartue综合-11-order FIR digital filter, verolog description, modelsim 6.0 through simulation, Quartue integrated
Update : 2024-05-20 Size : 1024 Publisher : shenyunfei
【VHDL-FPGA-Verilog】 4VerilogFIFO DL : 0: 一种新的FIFO实现方法,verilog描述，通过modelsim 6.0 仿真，Quartue综合-FIFO realize a new method, verilog description, modelsim 6.0 through simulation, Quartue integrated
Update : 2024-05-20 Size : 2048 Publisher : shenyunfei
【VHDL-FPGA-Verilog】 89_full_adder DL : 0: full adder设计代码，verilog 语言描述，通过modelsim 仿真，quartus综合-full adder design code, verilog language to describe, through the ModelSim simulation, quartus integrated
Update : 2024-05-20 Size : 4096 Publisher : shenyunfei
【VHDL-FPGA-Verilog】 Modelsim_timing_simulation_library DL : 0: 文章论述如何将向modelsim中添加仿真库，包括添加xilinx,altera,actel公司的仿真库的方法-Article on how to add ModelSim simulation library, including the add xilinx, altera, actel the company
Update : 2024-05-20 Size : 114688 Publisher : zhurui
【VHDL-FPGA-Verilog】 modelsim6.0 DL : 0: 使用說明對於modelsim的如何操作和使用及安裝的如何安裝-ModelSim for use of how to operate and use and installation of how to install
Update : 2024-05-20 Size : 388096 Publisher : kkk
【VHDL-FPGA-Verilog】 DSP_BUILDER_DESIGN DL : 0: DSP Builder设计初步,介绍Matlab/DSP Builder及其设计流程，正弦信号发生器完整的设计过程，以及使用Matlab、quartusII\modelsim详细的仿真过程。-DSP Builder preliminary design, introduce Matlab/DSP Builder and its design flow, sinusoidal signal generator complete design process, and the use of Matlab, quartusIImodelsim detailed simulation.
Update : 2024-05-20 Size : 1370112 Publisher : yehui
【VHDL-FPGA-Verilog】 modelsim DL : 0: 基于存储器的基4按频率抽取的fft 的vhdl描述可以对连续数据流进行256点的fft -Memory based on the base 4 by the frequency of fft taken the VHDL description of the continuous data stream can be carried out 256 point fft
Update : 2024-05-20 Size : 22528 Publisher : 庞志勇
【VHDL-FPGA-Verilog】 1_070109140434 DL : 0: modelsim 的使用教程，很详细讲解很清楚-the use of ModelSim Tutorial, in great detail to explain very clearly
Update : 2024-05-20 Size : 362496 Publisher :
【VHDL-FPGA-Verilog】 modelsimstudy DL : 0: 关于MODELSIM的学习资料希望对大家有用 -Of learning materials on the ModelSim hope useful for everyone
Update : 2024-05-20 Size : 593920 Publisher : 思根

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