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Search - FIR - List
【
DSP program
】
lab0501-FIR
DL : 0
TI DSP 5416 有限冲击FIR数字滤波器 设计例程-TI DSP 5416 a limited impact on the design of FIR digital filter routine
Update
: 2024-05-03
Size
: 11264
Publisher
:
陈洲
【
Windows Develop
】
fir
DL : 0
c语言实现的FIR滤波器,用户输入FIR滤波器的参数。-c language of the FIR filter, FIR filter user input parameters.
Update
: 2024-05-03
Size
: 206848
Publisher
:
wangzhen
【
VHDL-FPGA-Verilog
】
fir
DL : 0
code for fir filter see it is from altera site.-code for fir filter see it is from altera site.
Update
: 2024-05-03
Size
: 26624
Publisher
:
bris
【
Embeded-SCM Develop
】
fir
DL : 0
使用verilog语言实现的fir滤波器,使用了内部的触发器资源,优化。-Verilog language used to achieve the fir filter, the use of internal resources of the flip-flop, and optimize.
Update
: 2024-05-03
Size
: 1024
Publisher
:
liang jianbing
【
DSP program
】
FIR
DL : 0
在TMS320VC5509中,FIR滤波器的信号滤波-In TMS320VC5509 in, FIR filter signal filtering
Update
: 2024-05-03
Size
: 1024
Publisher
:
张苹
【
VHDL-FPGA-Verilog
】
fir
DL : 0
利用VHDL语言,设计了一个11阶的FIR滤波器。简单易懂-The use of VHDL language, designed a 11-order FIR filter. Easy to understand. .
Update
: 2024-05-03
Size
: 1024
Publisher
:
关小
【
VHDL-FPGA-Verilog
】
FIR
DL : 0
FIR of 1024 stage. 面向alteraFPGA器件设计-FIR of 1024 stage
Update
: 2024-05-03
Size
: 157696
Publisher
:
佴立峰
【
Other
】
fir
DL : 0
adsp bf533 实现 fir滤波的简单例程-bf533 achieve fir filtering routines
Update
: 2024-05-03
Size
: 78848
Publisher
:
徐海洋
【
VHDL-FPGA-Verilog
】
FIR
DL : 0
fir filter design using vhdl codes
Update
: 2024-05-03
Size
: 1024
Publisher
:
gowtham
【
VHDL-FPGA-Verilog
】
fir
DL : 0
16阶FIR VHDL程序并附带testbench,并有简单流水线设计!-16 Tap FIR vhdl code with testbench and pipelining design
Update
: 2024-05-03
Size
: 352256
Publisher
:
hongwan
【
VHDL-FPGA-Verilog
】
FIR
DL : 0
FIR滤波器的VHDL源代码及测试文件,已通过编译仿真,绝对正确。-FIR filter VHDL source code and test files, has passed the compiled simulation, absolutely correct.
Update
: 2024-05-03
Size
: 4096
Publisher
:
周州
【
DSP program
】
FIR
DL : 0
FIR低通滤波器,已在DSP试验箱上测试通过,希望对大家有帮助-FIR low-pass filter has been tested in the DSP chamber passed, want to help everyone
Update
: 2024-05-03
Size
: 1024
Publisher
:
小豆
【
DSP program
】
fir
DL : 0
fir dsp 的程序,经典的,不得不看-fir dsp programs, classic, and had to look at
Update
: 2024-05-03
Size
: 7168
Publisher
:
xaoi
【
DSP program
】
fir
DL : 0
先用matlab得到所需滤波器的系数,将AD采样的数据经过fir滤波器后输出-First to use matlab to obtain the required filter coefficients, data from the AD sample, after the output filter through the fir
Update
: 2024-05-03
Size
: 2262016
Publisher
:
潘存华
【
DSP program
】
FIR
DL : 0
FIR滤波器在DSP TMS320C5402上的实现(C语言和汇编语言实现)-FIR filter in the DSP TMS320C5402 implementation (C and assembly language implementation)
Update
: 2024-05-03
Size
: 61440
Publisher
:
万文亮
【
DSP program
】
FIR
DL : 0
用DSP来实现FIR滤波器。vectors.asm为汇编文件,main.c为主文件。-FIR filters with the DSP to achieve. vectors.asm for the compilation, main.c main document.
Update
: 2024-05-03
Size
: 450560
Publisher
:
roar
【
DSP program
】
fir
DL : 0
窗口法设计fir低通滤波器matlab程序-Low-pass filter design fir
Update
: 2024-05-03
Size
: 1024
Publisher
:
张坤
【
VHDL-FPGA-Verilog
】
fir-c2h
DL : 0
基于fpga的fir滤波器的设计 非常好,谢谢大家分享-fir filter design base on fpga it is very good
Update
: 2024-05-03
Size
: 11264
Publisher
:
gary
【
DSP program
】
fir
DL : 0
基于SIMULINK中的DSPbuilder搭建的fir滤波器,可以任意修改阶数。系数需要自己填-Based on SIMULINK in DSPbuilder erected fir filters, you can arbitrarily modify the order of. Fill factor needs its own
Update
: 2024-05-03
Size
: 11264
Publisher
:
郑程
【
Books
】
fir
DL : 0
本文以软件无线电为指导,提出基于CORDIC算法利用FPGA平台数字下变频器设计方案。首先分析下变频器的结构;然后采用模块化设计思想,将数字下变 频的功能模块包括数字控制振荡器、CIC抽取滤波、HBF抽取滤波器、FIR低通滤波器进行分析和FPGA的设计;最后在 MATLAB/DSPBuilder下硬件仿真模块进行仿真并给出仿真结果。-In this paper, software-defined radio as the guidance, based on the CORDIC algorithm uses the FPGA platform, digital down-converter design. First analyzes the structure of down-converter and then use a modular design concept, the digital down-conversion function modules including digital controlled oscillator, CIC decimation filtering, HBF decimation filter, FIR low-pass filter for analysis and FPGA design the final In the MATLAB/DSPBuilder under the hardware emulation module simulation and simulation results.
Update
: 2024-05-03
Size
: 201728
Publisher
:
jiang
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