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【Other】 crc DL : 0: 添加不同校验比特个数下的CRC校验，包括8，16，24个校验比特-Different number of parity bits added under the CRC checksum, parity bits, including 8,16,24 months
Update : 2024-05-18 Size : 2048 Publisher : 朱敏
【matlab】 CRC DL : 0: CRC check for WLN frame word！
Update : 2024-05-18 Size : 1024 Publisher : 杨涛
【VHDL-FPGA-Verilog】 CRC DL : 0: 循环冗余码实现，用Verilog语言实现的，希望和大家分享-CRC implementation, using Verilog language, and would like to share
Update : 2024-05-18 Size : 76800 Publisher : 叶亮
【Crack Hack】 CRC-16Code DL : 0: CRC-16是检测数据在发送过程中发生错误的常用校验方法，本文通过从工程应用的角度，讲述如何实现CRC-16的程序开发，并给出了Visual Basic和Visual C++程序代码，给从事工业控制的人员在写通信程序的时候提供一些有价值的参考。-CRC-16 is to detect data errors in the process of sending commonly used calibration methods, the paper from the engineering point of view, about how to implement CRC-16 program development, and gives the Visual Basic and Visual C++ code, to engage in industrial control personnel when the communication program in writing to provide some valuable information.
Update : 2024-05-18 Size : 29696 Publisher : kkk
【VHDL-FPGA-Verilog】 crc DL : 0: crc校验，是用于编码中的一种校验方法，这是书本中学习的方法-crc check is a check for the encoding method, which is the method book to learn
Update : 2024-05-18 Size : 4096 Publisher : luozhiyuan
【Algorithm】 crc DL : 0: 自动完成CRC校验码的计算 1 010110001101 110011 可以得到: (1)index:5 pointing:1 101011 110011 011000 (2)index:6 pointing:0 110000 110011 000011 (3)index:7 pointing:0 000110 0 000110 (4)index:8 pointing:0 001100 0 001100 (5)index:9 pointing:1 011001 0 011001 (6)index:10 pointing:1 110011 110011 000000 (7)index:11 pointing:0 000000 0 000000 (8)index:12 pointing:1 000001 0 000001 -CRC check code automatically derive the 1-1,010,110,001,101,110,011 can be: (1) index: 5 pointing: 1 101011 110011 011000 (2) index: 6 pointing: 0 110000 110011 000011 (3) index: 7 pointing: 0 000110 0 000110 (4) index: 8 pointing: 0 001100 0 001100 (5) index: 9 pointing: 1 011001 0 011001 (6) index: 10 pointing: 1 110011 110011 000000 (7) index: 11 pointing: 0 000000 0 000000 (8 ) index: 12 pointing: 1 000001 0 000001
Update : 2024-05-18 Size : 1024 Publisher : 夏治文
【VHDL-FPGA-Verilog】 crc-gen DL : 0: CRC Generator is a command-line application that generates Verilog or VHDL code for CRC of any data width between 1 and 1024 and polynomial width between 1 and 1024. The code is written in C and is cross-platform compatible
Update : 2024-05-18 Size : 60416 Publisher : badfox
【matlab】 CRC DL : 0: CRC校验，实现基本的CRC校验功能，当mask不同时，修改也相当方便-CRC checksum, CRC checksum to achieve the basic function, when the mask is not the same time, changes are also very convenient
Update : 2024-05-18 Size : 3072 Publisher : 张伟峰
【Voice Compress】 crc DL : 0: CRC code for CCIT 16 CRC
Update : 2024-05-18 Size : 3072 Publisher : ahsanhijazi
【Other Embeded program】 CRC.ZIP DL : 0: Example CRC check inorder write/read memory
Update : 2024-05-18 Size : 5120 Publisher : Ninoslav
【Linux-Unix】 CRC DL : 0: 这是在qt下实现的crc检验程序，是在xp下验证过了的，直接使用即可-This is achieved under the qt crc testing procedure is verified in the next xp, direct use can be
Update : 2024-05-18 Size : 768000 Publisher : mehewen
【Windows Develop】 8bit.CRC.checksum.algorithm32bit DL : 0: CRC校验8位16位32位算法设计经典代码8-bit CRC checksum algorithm 16-bit 32-bit classic code -8-bit CRC checksum algorithm 16-bit 32-bit classic code
Update : 2024-05-18 Size : 177152 Publisher : lili
【VHDL-FPGA-Verilog】 CRC DL : 0: CRC循环校验码的生成。文件里是（40，32）的校验码生成电路，采用串行输入、串行输出的方式。-CRC checksum generation cycle. File is (40,32) of the check code generation circuit, the use of serial input, serial output mode.
Update : 2024-05-18 Size : 143360 Publisher : 李雪茹
【VHDL-FPGA-Verilog】 CRC DL : 0: CRC校验参考设计Verilog代码包括所有代码-Verilog code for CRC check reference design includes all the code
Update : 2024-05-18 Size : 10240 Publisher : xuzunlei
【JSP/Java】 crc DL : 0: JAVA 编写的CRC循环冗余校验码，分两个文件，一个为生成发送信息的，一个为检验收到信息是否正确的-Written in JAVA CRC cyclic redundancy check code in two files, one to send the information to generate a receipt for the inspection information is correct
Update : 2024-05-18 Size : 1024 Publisher : 王雪琼
【matlab】 CRC DL : 0: 通过学习CRC编码原理，本部分建立了SIMULINk模型，实现了CRC编译码。-in this part we build the simulink modol of the encoded and decoded of CRC.we can more understand the code
Update : 2024-05-18 Size : 8192 Publisher : jie zhang
【Other】 CRC-C-Source DL : 0: CRC校验原理及其C语言实现CRC校验原理及其C语言实现-CRC checking principle and C language realization，CRC checking principle and C language realization
Update : 2024-05-18 Size : 9216 Publisher : jnhoodlum
【Other】 crc DL : 0: 实现模2除法生成crc码和校验在一台机器上生成另外一台机器上校验-Implement modulo 2 division generated code and the crc checksum generated on one machine on another machine check
Update : 2024-05-18 Size : 344064 Publisher : 郭炳龙
【Program doc】 CRC.txt DL : 0: 用查表法计算CRC码 C的程序设计，生成多项式为CRC-CCITT -CRC look-up table method using C programming code, generating polynomial for the CRC-CCITT
Update : 2024-05-18 Size : 58368 Publisher : lfzxyy
【VHDL-FPGA-Verilog】 CRC-Generator-for-Verilog-or-VHDL DL : 0: CRC Generator for Verilog or VHDL-CRC Generator for Verilog or VHDL
Update : 2024-05-18 Size : 3072 Publisher : wz

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